基于错误特征的NAND Flash存储策略研究

发布时间：2019-06-09 17:26

【摘要】：NAND Flash凭借非易失、读写速度快、存储容量大、功耗低以及抗震性好等优良特性,在大容量与高采样率测试系统中得到了广泛的应用。为进一步提高NAND Flash的存储容量和降低其单元存储成本,NAND Flash芯片的尺寸随着半导体生产工艺的提高而持续减小。但是NAND Flash存储胞元内相邻两个阈值电压间隔的逐渐减小带来了数据错误率的升高。由于存储胞元仅能承受有限次数的编程/擦除周期,所以导致了NAND Flash有限的使用寿命。因此,研究相关的NAND Flash存储管理策略以降低其错误率和延长其使用寿命将变得非常有意义。本文以NAND Flash的错误特征为基础,依次从编程数据预处理、Flash转换层(Flash Translation Layer,FTL)算法优化、平均错误率预测模型以及页粒度可实现的磨损均衡等方面对NAND Flash存储系统的管理策略进行了研究,并在硬件平台上进行了相关的实验验证。本文的主要研究内容和取得的成果如下:1.为降低NAND Flash的主要错误率,本文首先研究了NAND Flash的数据驻留与编程干扰错误所具有的明显的数据相关性,然后提出了一种基于数据模式差异的联合编码策略。该策略的核心是通过一种重映射编码提升待编程数据中“1”的比例,并依托于缩短BCH码构成联合编码构架对重映射编解码过程中的数据进行保护。由于该联合编码策略不会造成编解码前后有效数据宽度的变化因而不会占用额外的用户数据区,所以该策略能够实现与各种FTL算法的透明适配。实验结果表明,本文所提出的联合编码策略可以在数据吞吐率略有下降的情形下,使NAND Flash的编程干扰和数据驻留错误分别降低约90%和98%。2.为提高NAND Flash的使用寿命,本文首先研究了NAND Flash驻留错误所表现出来的显著页差异性,然后提出了一种新颖的关注页耐受力差异(Page Endurance Variance Aware,PEVA)的FTL优化策略。PEVA策略将传统的FTL地址映射原理与坏块管理的构架进行了融合与优化,将运行于底层驱动层的粗粒度的坏块管理转化为融入FTL层的细粒度的坏页管理,以充分挖掘NAND Flash数据块内各页的使用寿命潜能。实验结果表明,与传统坏块管理算法相比,PEVA策略可以在不增加额外硬件负荷的情况下,使NAND Flash寿命最大延长9.8倍。3.本文详细分析了NAND Flash随驻留时间和编程/擦除次数表现出来的错误特征,在此基础上总结出一种基于多项式的页原始平均位错误率预测模型。依托于该模型,并结合NAND Flash存在的页耐受力差异性,本文提出了一种细粒度可实现的页磨损均衡(Page-Granularity Wear-Leveling,PGWL)策略。PGWL策略可以根据NAND Flash错误率预估模型对数据页的错误率等级进行评判,并以此作为衡量标准来实时地、动态地实施编程释放操作。实验结果表明,PGWL策略与传统的块级磨损均衡策略相比,能够延长NAND Flash的使用寿命约87.8%,而其带来的数据吞吐负荷可以忽略不计。
[Abstract]:NAND Flash has been widely used in large capacity and high sampling rate test systems because of its excellent characteristics, such as non-easy to lose, fast reading and writing speed, large storage capacity, low power consumption and good seismic resistance. In order to further improve the storage capacity of NAND Flash and reduce its unit storage cost, the size of, NAND Flash chip continues to decrease with the increase of semiconductor production process. However, the gradual decrease of the voltage interval between the two adjacent threshold cells in NAND Flash storage cells leads to the increase of data error rate. Because the storage cell can only withstand a limited number of programming / erasure cycles, it leads to the limited service life of NAND Flash. Therefore, it is very meaningful to study the related NAND Flash storage management strategies to reduce its error rate and prolong its service life. Based on the error characteristics of NAND Flash, this paper optimizes the algorithm from programming data preprocessing and Flash conversion layer (Flash Translation Layer,FTL). The average error rate prediction model and the wear balance of page granularity are studied, and the management strategy of NAND Flash storage system is studied, and the related experiments are carried out on the hardware platform. The main research contents and achievements of this paper are as follows: 1. In order to reduce the main error rate of NAND Flash, this paper first studies the obvious data correlation between NAND Flash data residence and programming interference error, and then proposes a joint coding strategy based on data pattern difference. The core of this strategy is to improve the proportion of "1" in the data to be programmed through a kind of remapping coding, and to protect the data in the process of remapping coding and decoding by shortening the joint coding framework of BCH code. Because the joint coding strategy does not cause the change of the effective data width before and after coding and decoding, it will not occupy the additional user data area, so the strategy can realize the transparent adaptation with various FTL algorithms. The experimental results show that the joint coding strategy proposed in this paper can reduce the programming interference and data resident error of NAND Flash by about 90% and 98% respectively when the data throughput decreases slightly. In order to improve the service life of NAND Flash, this paper first studies the significant page difference of NAND Flash resident error, and then proposes a novel concern page tolerance difference (Page Endurance Variance Aware,. The FTL optimization strategy of PEVA). The PEVA strategy merges and optimizes the traditional FTL address mapping principle and the framework of bad block management, and converts the coarse-grain bad block management running in the underlying driver layer into the fine-granularity bad page management integrated into the FTL layer. In order to fully tap the useful life potential of each page in the NAND Flash data block. The experimental results show that compared with the traditional bad block management algorithm, PEVA strategy can prolong the life of NAND Flash by 9. 8 times without increasing the additional hardware load. In this paper, the error characteristics of NAND Flash with resident time and programming / erasure times are analyzed in detail, on the basis of which a prediction model of page original average bit error rate based on multinomial is summarized. Based on this model and the difference of page tolerance in NAND Flash, a fine granularity and realizable page wear equilibrium (Page-Granularity Wear-Leveling,) is proposed in this paper. PGWL) Strategy. PGWL strategy can judge the error rate level of data page according to the NAND Flash error rate prediction model, and use it as a measure to implement programming release operation in real time and dynamically. The experimental results show that compared with the traditional block wear equilibrium strategy, PGWL strategy can prolong the service life of NAND Flash by about 87.8%, and the data throughput load can be ignored.
【学位授予单位】：哈尔滨工业大学
【学位级别】：博士
【学位授予年份】：2016
【分类号】：TP333

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