应用于TD-LTE-Advanced终端的模数转换器的研究与设计

发布时间：2018-02-20 17:11

本文关键词： 逐次逼近型模数转换器桥接电容比较器失调校正时分复用　出处：《复旦大学》2013年硕士论文　论文类型：学位论文

【摘要】：TD-LTE-Advanced (Time Division-Long Term Evolution-Advanced)是中国具有自主知识产权的第四代运动无线通讯技术。它吸纳了TD-SCDMA的主要技术元素,体现了我国通信产业界在宽带无线移动通讯领域的最新自主创新成果。TD-LTE-Advanced技术的提出,保证了中国在4G无线通讯领域具有核心竞争力,维护了我国在日益激烈的国际竞争中的国家安全,具有非常重要的战略意义和经济价值。本文针对TD-LTE-Advanced技术设计了一款高速高精度低功耗的模数转换器,完成了从系统架构分析、系统建模仿真、电路模块仿真、系统整体电路仿真、版图及提取寄生参数后仿真和硬件实现以及测试验证的整个流程。该模数转换器采用逐次逼近型模数转换器(Successive Approximation Register, SAR ADC)结构,在保证所需的转换速度的同时,能够有效的减小芯片面积,降低功耗,从而节省芯片的成本。该SAR ADC采用了顶级板采样技术,从而省掉了DAC的最高位电容,将采样电容缩小到只需要传统结构的1/2；优化了DAC的桥接电容结构,低位(Least Significant Bits, LSBs)为4bits,高位(Most Significant Bits, MSBs)为7位,有效的减小了LSBs寄生电容对DAC线性度的影响；系统分析了桥接电容结构对DAC线性的影响的分析,并推导了相关公式,提出了一种有效解决LSBs寄生电容影响线性度的解决方法；基于时分复用技术和异步复位思想,提出了一种新颖的控制逻辑,只需要传统结构一半的硬件电路便能实现相同的功能,极大的降低了系统功耗；提出了一种全新的比较器失调电压校正技术,取代传统所采用的预放大电路,来降低比较器的失调电压,有效的解决了比较器低功耗和高精度之间的矛盾。该模数转换器芯片采用SMIC65nm,1.2V,1P8M(单层多晶,8层金属)CMOS混合信号工艺实现,有效面积为0.3x0.2mm2,功耗为2.4mW。版图后仿真结果表明,在50MHz采样率时的最高信噪比(SINDR)为71.5dB,无杂散动态范围(SFDR)为84.5dB, FoM为15.2fJ/conversion。
[Abstract]:TD-LTE-Advanced time Division-Long Term Evolution-Advanced is a 4th generation mobile wireless communication technology with independent intellectual property rights in China. It absorbs the main technical elements of TD-SCDMA. It reflects the latest independent innovation in the field of broadband wireless mobile communication. TD-LTE-Advanced technology is put forward, which ensures that China has the core competitiveness in 4G wireless communication field. Maintaining our country's national security in the increasingly fierce international competition has very important strategic significance and economic value. In this paper, a high speed, high precision and low power A / D converter is designed for TD-LTE-Advanced technology, which includes system architecture analysis, system modeling and simulation, circuit module simulation, and whole system circuit simulation. Layout and extraction of parasitic parameters after simulation and hardware implementation as well as the entire process of test verification. The analog-to-digital converter uses successive approximation analog-to-digital Approximation register (SAR ADC) structure, which can effectively reduce the chip area and power consumption while ensuring the required conversion speed. The SAR ADC uses top-level board sampling technology, thus eliminating the maximum potential capacitance of DAC, reducing the sampling capacitance to only one half of the traditional structure, and optimizing the bridging capacitance structure of DAC. The low least Significant bits (LSBs) are 4 bits and the high cost Significant bits (MSBs) are 7 bits. The influence of parasitic capacitance of LSBs on the linearity of DAC is effectively reduced, and the influence of bridge capacitance structure on the linearity of DAC is systematically analyzed, and the relevant formulas are derived. This paper presents an effective solution to the influence of LSBs parasitic capacitance on linearity, and proposes a novel control logic based on time-division multiplexing and asynchronous reset. Only half of the hardware circuit with traditional structure can achieve the same function, which greatly reduces the power consumption of the system. A new offset voltage correction technique of comparator is proposed to replace the traditional preamplifier circuit. In order to reduce the offset voltage of comparator, the contradiction between low power consumption and high precision of comparator is effectively solved. The analog to digital converter chip is realized by SMIC65nmP8M (single layer polycrystalline 8 layer metal layer CMOS mixed signal process). The effective area is 0.3x0.2mm2.The power consumption is 2.4mW.After layout, the simulation results show that, The maximum signal-to-noise ratio (SNR) is 71.5 dB at 50MHz sampling rate, the non-spurious dynamic range is 84.5 dB, and the FoM is 15.2fJ / r conversion.
【学位授予单位】：复旦大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TN792;TN929.5

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