AVS及H.264双模熵解码器的硬件设计

发布时间：2018-03-05 01:09

本文选题：AVS标准　切入点：H.264标准　出处：《山东大学》2013年硕士论文　论文类型：学位论文

【摘要】：H.264/AVC是由国际电信联盟和运动图像专家组联合制定的新一代视频压缩标准,被认为是当前最具影响力的视频标准。AVS标准是我国具有自主知识产权的第二代信源编码标准,近年得到国家的大力推广。在未来这两种标准必将互相融合,共同发展。熵编码是AVS和H.264中都采用的无损压缩编码技术,可以极大减小码流的冗余度,因此设计同时兼容这两种标准的双模熵解码器具有重要意义。本文首先对AVS及H.264标准进行研究并比较了其异同,然后详细分析了其中采用的熵编码算法,提出了AVS及H.264双模熵解码器的硬件结构,使其既支持AVS的CA-2D-VLC解码,又支持H.264的CAVLC解码和CABAC解码,增强了通用性。该结构复用了码流缓冲移位和指数哥伦布解码等模块,从而减小电路资源消耗；对AVS码表进行压缩优化,对H.264的码表进行了分割重组,降低了码表复杂度,提高了码表索引效率；采用了流水线结构加快了解码速度；使用组合逻辑电路查找码表,避免了对存储器的访问,减少了不必要的时序花销；CAVLC解码模块将Coffetoken解码与拖尾系数符号解码压缩在一个周期完成,并在解码Runbefore的同时重组残差块,节约了解码时钟；提出了高效的CABAC解码模块结构,采用双口RAM存储上下文模型,并设计了高效的算术解码计算模块,提高了CABAC解码速度。本文采用Verilog HDL完成了双模熵解码器的寄存器传输级设计,并根据AVS标准参考软件RM52j和H.264标准参考软件JM9.4建立了C参考模型。使用数字仿真工具VCS对熵解码器进行了功能仿真,并与参考模型的输出进行比对,验证了设计的正确性。采用TSMC的0.13um工艺库,通过Synopsys公司的Design Compiler逻辑综合工具对设计进行逻辑综合,结果表明该解码器可工作在77MHz时钟频率下,满足对4CIF、720p HD等格式视频的实时解码。最后采用形式验证工具Formality对综合生成的门级网表进行了形式验证。验证和综合结果表明,该双模熵解码器达到了本课题的设计目标。
[Abstract]:H.264 / AVC is a new generation video compression standard developed jointly by the International Telecommunication Union and the Motion Image expert Group. It is considered to be the most influential video standard. AVS is the second generation source coding standard with independent intellectual property rights in China. In the future, the two standards will be merged and developed together. Entropy coding is a lossless compression coding technique used in both AVS and H.264, which can greatly reduce the redundancy of the code stream. So it is important to design two-mode entropy decoders compatible with these two standards. In this paper, the AVS and H.264 standards are studied and compared, then the entropy coding algorithm is analyzed in detail, and the hardware structure of AVS and H.264 dual-mode entropy decoder is proposed to support the CA-2D-VLC decoding of AVS. It also supports the CAVLC decoding and CABAC decoding of H.264, and enhances the generality. The structure reuses several modules, such as stream buffer shift and exponential Columbus decoding, to reduce the consumption of circuit resources, and optimizes the compression of the AVS code table. The code table of H.264 is segmented and reorganized, which reduces the complexity of the code table and improves the efficiency of the code table index. Pipeline structure is used to speed up the decoding speed, and the combinational logic circuit is used to find the code table, thus avoiding the access to the memory. The Coffetoken decoding and trailing coefficient symbol decoding are compressed in one cycle, and the residual block is recombined while decoding the Runbefore, thus saving the decoding clock, and an efficient CABAC decoding module structure is proposed. The dual-port RAM memory context model is adopted and an efficient arithmetic decoding calculation module is designed to improve the speed of CABAC decoding. In this paper, the register transfer level of dual-mode entropy decoder is designed by using Verilog HDL, and the C reference model is established according to AVS standard reference software RM52j and H.264 standard reference software JM9.4. The function of entropy decoder is simulated with the digital simulation tool VCS. Compared with the output of the reference model, the correctness of the design is verified. The design is synthesized by Design Compiler logic synthesis tool of Synopsys Company by using 0.13um process library of TSMC. The results show that the decoder can work at 77MHz clock frequency. It satisfies the real-time decoding of 4CIF-720p HD format video. Finally, the gate network table generated by the synthesis is verified by the formal verification tool Formality. The verification and synthesis results show that the dual-mode entropy decoder achieves the design goal.
【学位授予单位】：山东大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TN919.8;TN764

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