数字雷达接收系统的SoC原型实现与验证

发布时间：2018-03-10 01:17

本文选题：数字雷达专用芯片　切入点：可编程门阵列　出处：《西安电子科技大学》2014年硕士论文　论文类型：学位论文

【摘要】：数字雷达系统由于其高精度幅相正交特性、抗干扰性、稳定性等优势已经成为新一代雷达体系的主要发展方向，被更多的应用到全天候远距离实现对目标的探测和定位，在军事民用领域如民航交通管制、陆海空监视、精确制导、导航、汽车防撞与测距以及气象预报等众多国民经济重要部门。同时在微电子技术日新月异的发展中，FPGA和DSP在信号处理能力上不断提升，ASIC即专用集成电路能够实现比DSP和FPGA处理速度更快，功耗更低及更高的可靠性，并拥有自主知识产权的芯片大规模化生产后在价格上具有很大的优势。因此利用最新的片上芯片系统（System on Chip）技术来设计新一代体制的数字雷达系统成为目前研究的当务之急。本论文的工作来源于部委研究项目，重点研究数字雷达接收机信号处理的IP核设计,并且就数据通路的性能优化、面积优化、验证平台等方面展开了研究和设计实现工作。主要讨论了流水式数字信号处理器和时分复用方式的电路实现架构。并在时分复用方式下对性能优化与电路优化两个方面进行讨论并设计了数据通路。并且最终实现了两个优化条件下的数据通路框架设计。本论文工作在雷达接收通道SoC原型系统设计实验和板级验证平台的实现基础上，对主要雷达信号进行了验证测试。测试数据结果表明功能满足要求。在SMIC0.13um工艺下，性能优化中最高中频信号吞吐率为2GSPS，，面积优化中数据通路面积约0.05mm2。实验结果说明本系统设计和验证平台达到了项目设计指标要求，为进一步SoC芯片实验奠定了良好的基础。
[Abstract]:The digital radar system has become the main development direction of the new generation radar system because of its high precision amplitude-phase orthogonality, anti-jamming, stability and so on. In military and civilian areas such as civil aviation traffic control, land, sea and air surveillance, precision guidance, navigation, At the same time, with the rapid development of microelectronics technology, FPGA and DSP continuously improve their signal processing capability, that is, ASIC can achieve better performance than DSP. And FPGA process faster, Lower power consumption and higher reliability, And the chip with independent intellectual property has a great advantage in price after large-scale production, so it is urgent to design a new generation of digital radar system by using the latest chip system system on chip Chiptechnology. The work of this paper comes from the research project of the ministry, focusing on the IP core design of digital radar receiver signal processing, and the performance optimization and area optimization of the data path. This paper mainly discusses the circuit implementation architecture of income type digital signal processor and time division multiplexing mode, and optimizes the performance and circuit under the time division multiplexing mode. Finally, the data path framework under two optimized conditions is designed. Based on the design experiment of radar receiving channel SoC prototype system and the realization of board level verification platform, the main radar signals are verified and tested. The test results show that the function meets the requirements. Under the SMIC0.13um technology, the main radar signals are verified and tested. In the performance optimization, the maximum if signal throughput is 2GSPS, and the data path area is about 0.05mm2.The experimental results show that the system design and verification platform meets the project design requirements, and lays a good foundation for further SoC chip experiments.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN957.5

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