基于虚拟化技术的SV验证平台研究

发布时间：2018-04-20 19:41

本文选题：片上系统 + CPU核　；参考：《西安电子科技大学》2014年硕士论文

【摘要】：近十年来,由于无线通信设备市场的强劲增长,使得移动通信基带芯片而受到广泛关注。随着片上系统(System on-chip,SoC)设计规模的增大和复杂性的增加,验证工作在数字电路中的地位变得越来越重要。本文基于通信基带SoC芯片的研发项目,对系统级验证中平台的设计和优化的问题进行了深入研究,给出了完整的优化解决方案和测试用例的分析。首先,通过介绍系统级验证平台基本功能和结构,具体分析了SystemVerilog验证平台的工作原理及其组件之间联系。在此基础上,针对现有验证平台的需求进行分析并提出优化设计目标。然后,根据优化目标提出具体优化设计方法,即部分硬件实体的抽象虚拟化,主要分为两部分:一方面是CPU(Central Processing Unit)的虚拟化,另一方面是总线功能模型的抽象。通过这两部分的虚拟模型来替换实体,简化设计。对于CPU的虚拟化,可以在验证平台上模拟CPU的行为建立一个模型cRunner,它能将测试用例的C程序转换成SV程序,直接在仿真器上执行。而cRunner与其他模块通信的总线模型,可采用开放核心协议(Open Core Protocol,OCP)和通用验证方法学(Universal Verification Methodology),设计一个总线功能模型OCP_agent,它能实现从cRunner到NoC的接口协议转换,从而对寄存器/存储器的进行访问。优化后的验证平台称为统一的验证平台(Unified Testbench,UTB)。在UTB上采用软硬件协同仿真策略,实现了仿真过程的加速和无核心系统下的仿真验证,达到了预期的优化设计目标。最后,在原有的验证平台和优化的验证平台分别进行测试用例的仿真,仿真包括系统级仿真和门级仿真。得出的数据结果,进行对比分析,实际物理仿真时间减少了83.9%。证明优化的验证平台能大幅加快仿真速度,提高验证效率。本论文的主要创新点包括:采用直接编程接口(Direct Programming Interface,DPI)能在C语言域和SV语言域中转换的特点,实现对CPU虚拟模型—cRunner的设计。它能把在实体CPU中的C程序直接转移到仿真器中,实现C程序的高效快速执行,使得BOOT时间减少了87.7%。使用UVM验证方法学,完成一个可扩展OCP总线功能模型的设计。在使用UVM过程中,采用了事务级建模、动态配置和内建工厂等机制。同时设计了一个OCP协议可配置的模块,扩大了该模型的应用范围。这些特性使得该模型作为验证知识产权(Intellectual Property,IP)兼具有良好的可复用性和扩展性。
[Abstract]:In the last decade, mobile communication baseband chips have attracted wide attention due to the strong growth of wireless communication equipment market. With the increase of design scale and complexity of on-chip system on-chip-SoC, verification becomes more and more important in digital circuits. Based on the research and development of communication baseband SoC chip, the design and optimization of platform in system-level verification are studied in this paper, and the complete optimization solution and test case analysis are given. Firstly, by introducing the basic function and structure of the system level verification platform, the working principle of the SystemVerilog verification platform and the relationship between its components are analyzed in detail. On this basis, the requirements of the existing verification platform are analyzed and the optimization design objectives are put forward. Then, according to the optimization goal, the concrete optimization design method is put forward, that is, the abstract virtualization of some hardware entities is divided into two parts: one is the virtualization of CPU(Central Processing Unit, the other is the abstraction of the bus function model. The virtual model of these two parts is used to replace the entity and simplify the design. For the virtualization of CPU, a model cRunner can be established by simulating the behavior of CPU on the verification platform. It can convert C programs of test cases into SV programs and execute directly on the simulator. The bus model of communication between cRunner and other modules can be designed by open core protocol (Open Core Protocol) and Universal Verification method. It can realize the interface protocol conversion from cRunner to NoC. Thus the register / memory is accessed. The optimized verification platform is called Unified Test bench. The hardware / software co-simulation strategy is adopted in UTB to accelerate the simulation process and verify the simulation under the no core system. The desired optimization design goal is achieved. Finally, the test cases are simulated on the original verification platform and the optimized verification platform. The simulation includes system level simulation and gate level simulation. The actual physical simulation time is reduced by 83.9. It is proved that the optimized verification platform can greatly accelerate the speed of simulation and improve the efficiency of verification. The main innovations of this thesis are as follows: the design of CPU virtual model -cRunner is realized by using direct Programming interface (DPI), which can be converted in C and SV language domains. It can transfer C program in entity CPU directly to the emulator, realize C program execution efficiently and quickly, and reduce the BOOT time by 87.7%. An extensible OCP bus function model is designed using UVM verification methodology. In the process of using UVM, the mechanism of transaction level modeling, dynamic configuration and built-in factory are adopted. At the same time, a configurable module of OCP protocol is designed, which expands the application range of the model. These characteristics make the model have good reusability and extensibility as well as verify intellectual property IPs.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN47

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