基于FPGA多核技术的AVS视频编码的设计与实现

发布时间：2018-06-24 08:32

本文选题：嵌入式系统 + 多核处理器　；参考：《北京工业大学》2013年硕士论文

【摘要】：目前的各类嵌入式设备普遍采用专用ASIC（Application Specific IntegratedCircuit）芯片实现视频编码的功能。其中H.264由于其具有高数据压缩率以及友好的网络亲和性，，在众多的视频编码ASIC中得到了广泛的支持，也使其在各类视频编码产品中得到了广泛的应用。但是受知识产权的制约，国内厂商每年都要为此支付一笔高额的专利费用。针对这一问题我国推出了具有自主知识产权的音视频压缩标准AVS（Audio Video coding Standard），它采用1元钱专利池方式，只对AVS编解码产品收费，且额度为每台设备1元人民币。与H.264/AVC相比，AVS标准不仅降低了专利费，更重要的是在编码性能与H.264基本相当的情况下，其复杂度也得到了一定程度的降低。但是目前支持AVS编码的专用芯片还很少，因而制约了其在嵌入式处理器平台上的广泛应用。为了提高AVS在嵌入式平台上的编码速度，本文在研究基于FPGA多核系统的基础上，实现了AVS的并行算法，具体工作包括研究了AVS编码过程以及其官方参考模型RM52j，将该算法进行修改，使其可以移植到XilinxXUPV5-LX110T芯片上。实验结果表明，该算法对于嵌入式单核系统而言，极高的复杂度使得其根本无法服务于人们的生活。其次，针对AVS编码过程进行改进，设计并实现了一种AVS帧组级并行算法，搭建了适合于该算法的3核嵌入式结构。实验结果表明，在编码性能几乎不变的情况下，该算法可以在该3核体系结构上的加速比达到了1.786。最后，为了进一步提高编码速度，设计并实现了一种AVS改进帧级并行算法，该算法采用混合并行粒度，对于帧内编码采用宏块级并行，对于帧间编码采用帧级并行。搭建了宏块级2路并行，帧级3路并行的多核嵌入式系统结构。实验结果表明，该算法可以在压缩性能几乎不变的情况下实现加速，加速比为4.499。帧组级并行算法为ASIC芯片实现AVS视频编码提供了良好的参考。改进帧级并行算法为多FPGA实现视频编码提供了一个很好的方案。
[Abstract]:At present, all kinds of embedded devices generally use ASIC (Application specific Integrated Circuit) chip to realize video coding. Because of its high data compression ratio and friendly network affinity, H.264 has been widely supported in many ASIC video coding, and has been widely used in various video coding products. However, due to intellectual property rights, domestic manufacturers pay a high patent fee every year. In order to solve this problem, Audio Video coding Standard (AVS), which has independent intellectual property rights, has been developed in China. It adopts a 1 yuan patent pool and charges only for the codec products of AVS, and its quota is 1 yuan per unit. Compared with H.264 / AVC, the AVS standard not only reduces the patent fee, but also reduces the complexity to a certain extent when the coding performance is basically equivalent to that of H. 264. However, there are few special chips supporting AVS coding, which restricts its wide application on embedded processor platform. In order to improve the coding speed of AVS on embedded platform, the parallel algorithm of AVS is realized on the basis of studying the multi-core system based on FPGA. The detailed work includes the study of AVS coding process and its official reference model RM52j. the algorithm is modified so that it can be transplanted to Xilinx XUPV5-LX110T chip. Experimental results show that the algorithm can not serve people's lives because of its high complexity. Secondly, an AVS frame group level parallel algorithm is designed and implemented to improve the AVS coding process, and a 3-core embedded structure suitable for the algorithm is built. The experimental results show that the speedup ratio of the algorithm can reach 1.786 on the three core architecture when the coding performance is almost the same. Finally, in order to further improve the coding speed, an improved frame level parallel algorithm of AVS is designed and implemented. The algorithm adopts mixed parallel granularity, macro block level parallel for intra-frame coding and frame level parallel for inter-frame coding. A multi-core embedded system architecture with two parallel channels at macroblock level and three parallel channels at frame level is built. The experimental results show that the proposed algorithm can be accelerated with a speedup ratio of 4.499 when the compression performance is almost constant. Frame group level parallel algorithm provides a good reference for ASIC chip to implement AVS video coding. The improved frame-level parallel algorithm provides a good scheme for multi-FPGA video coding.
【学位授予单位】：北京工业大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TN919.81

【相似文献】