多位∑-Δ模数转换技术研究
发布时间：2018-10-13 12:08
【摘要】：Σ-Δ模数转换器因其线性度好、精度高、功耗低等优点而被广泛应用在视频、多媒体、地震勘测仪器、声纳、电子测量和中等分辨率的系统中。目前，多位量化的高精度Σ-Δ模数转换技术是人们研究的热点，而国内在模数转换器方面的研究还处于开始起步阶段。对Σ-Δ模数转换器体系结构的研究和设计水平与国外的先进水平相比存在很大差距，需要我们加强在Σ-Δ模数转换技术上的研发力度，研究拥有自主知识产权的Σ-Δ模数转换器。因此，对多位Σ-Δ模数转换技术的研究无论在学术上还是经济上都有着非常重要的意义。 本文详细阐述了Σ-Δ型转换器的基本原理、结构以及多位量化Σ-Δ模数转换器设计的关键技术。在研究Σ-Δ型模数转换器各种结构的基础上，重点研究了多位量化结构，讨论了多位量化器位数与Σ-Δ模数转换器精度的关系。并利用多位量化Σ-Δ模数转换技术设计了24位多位量化Σ-Δ模数转换器。 在系统级设计过程中，，首先是Σ-Δ调制器的系统设计，根据Σ-Δ调制器的相关知识，确定了Σ-Δ调制器的参数和结构，并运用MALTAB和Simulink进行了建模和仿真验证，确定Σ-Δ调制器为三位量化的单环三阶CIFB (Cascade-of-integrators, feed-back form)结构，过采样率为256。其次是数字抽取滤波器，根据Σ-Δ调制器的性能要求选择了数字抽取滤波器的结构与类型，整个抽取滤波器采用梳状滤波器和两级半带滤波器级联的结构实现。依据系统性能的要求，在MALTAB中设计了梳状滤波器和半带滤波器。最后，在Simulink中搭建了多位Σ-Δ模数转换器的系统模型并进行了仿真，由仿真结果可知，本文所设计的多位Σ-Δ模数转换器有效位数为24bit，信噪比为144dB，验证了多位量化结构的合理性。 通过对多位Σ-Δ模数转换器的系统级设计，确定了Σ-Δ调制器和数字抽取滤波器的设计参数及结构，依据这些参数，选择合适的器件和运算放大器，通过分立元器件对Σ-Δ调制器进行了电路设计，包括三阶积分器、3bit量化器和3bit反馈DAC；在FPGA上进行了数字抽取滤波器的实现，编写了数字抽取滤波器的Verilog代码。
[Abstract]:危-螖 A / D converters are widely used in video, multimedia, seismic survey instruments, sonar, electronic measurement and medium resolution systems because of their good linearity, high accuracy and low power consumption. At present, the high precision 危-螖 A / D conversion technology with multi-bit quantization is a hot topic, but the research on ADC in China is still in its infancy. The research and design level of 危-螖 A / D converter architecture is quite different from that of foreign advanced level. We need to strengthen the R & D of 危-螖 A / D converter and study 危-螖 A / D converter with independent intellectual property rights. Therefore, the research on the technology of multi-bit 危-螖 A / D conversion is of great significance in both academic and economic aspects. In this paper, the basic principle and structure of 危-螖 converter and the key technology in the design of multi bit quantization 危-螖 A / D converter are described in detail. On the basis of studying the various structures of 危-螖 A / D converter, the multibit quantization structure is emphatically studied, and the relationship between the bit number of multi bit quantizer and the precision of 危-螖 A / D converter is discussed. A 24-bit multibit 危-螖 A / D converter is designed by using the multibit 危-螖 ADC technology. In the process of system-level design, the first is the system design of 危-螖 modulator. According to the relevant knowledge of 危-螖 modulator, the parameters and structure of 危-螖 modulator are determined, and the modeling and simulation are done by using MALTAB and Simulink. It is determined that the 危-螖 modulator is a three-bit quantized single-ring third-order CIFB (Cascade-of-integrators, feed-back form) structure with a over-sampling rate of 256. Secondly, digital decimation filter. According to the performance requirement of 危-螖 modulator, the structure and type of digital decimation filter are selected. The whole decimation filter is realized by the structure of comb filter and two-stage half-band filter cascade. According to the requirement of system performance, comb filter and half band filter are designed in MALTAB. Finally, the system model of multi-bit 危-螖 A / D converter is built and simulated in Simulink. The simulation results show that the effective bit number and signal-to-noise ratio of the designed multi bit 危-螖 A / D converter are 24 bits and 144 dB, which verifies the rationality of the multibit quantization structure. The design parameters and structure of 危-螖 modulator and digital decimation filter are determined by the system-level design of multi-bit 危-螖 A / D converter. According to these parameters, appropriate devices and operational amplifiers are selected. The circuit of 危-螖 modulator is designed by discrete components, including third-order integrator, 3bit quantizer and 3bit feedback DAC;. The digital decimation filter is implemented on FPGA, and the Verilog code of digital decimation filter is written.
【学位授予单位】：哈尔滨理工大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN792
本文编号：2268563
[Abstract]:危-螖 A / D converters are widely used in video, multimedia, seismic survey instruments, sonar, electronic measurement and medium resolution systems because of their good linearity, high accuracy and low power consumption. At present, the high precision 危-螖 A / D conversion technology with multi-bit quantization is a hot topic, but the research on ADC in China is still in its infancy. The research and design level of 危-螖 A / D converter architecture is quite different from that of foreign advanced level. We need to strengthen the R & D of 危-螖 A / D converter and study 危-螖 A / D converter with independent intellectual property rights. Therefore, the research on the technology of multi-bit 危-螖 A / D conversion is of great significance in both academic and economic aspects. In this paper, the basic principle and structure of 危-螖 converter and the key technology in the design of multi bit quantization 危-螖 A / D converter are described in detail. On the basis of studying the various structures of 危-螖 A / D converter, the multibit quantization structure is emphatically studied, and the relationship between the bit number of multi bit quantizer and the precision of 危-螖 A / D converter is discussed. A 24-bit multibit 危-螖 A / D converter is designed by using the multibit 危-螖 ADC technology. In the process of system-level design, the first is the system design of 危-螖 modulator. According to the relevant knowledge of 危-螖 modulator, the parameters and structure of 危-螖 modulator are determined, and the modeling and simulation are done by using MALTAB and Simulink. It is determined that the 危-螖 modulator is a three-bit quantized single-ring third-order CIFB (Cascade-of-integrators, feed-back form) structure with a over-sampling rate of 256. Secondly, digital decimation filter. According to the performance requirement of 危-螖 modulator, the structure and type of digital decimation filter are selected. The whole decimation filter is realized by the structure of comb filter and two-stage half-band filter cascade. According to the requirement of system performance, comb filter and half band filter are designed in MALTAB. Finally, the system model of multi-bit 危-螖 A / D converter is built and simulated in Simulink. The simulation results show that the effective bit number and signal-to-noise ratio of the designed multi bit 危-螖 A / D converter are 24 bits and 144 dB, which verifies the rationality of the multibit quantization structure. The design parameters and structure of 危-螖 modulator and digital decimation filter are determined by the system-level design of multi-bit 危-螖 A / D converter. According to these parameters, appropriate devices and operational amplifiers are selected. The circuit of 危-螖 modulator is designed by discrete components, including third-order integrator, 3bit quantizer and 3bit feedback DAC;. The digital decimation filter is implemented on FPGA, and the Verilog code of digital decimation filter is written.
【学位授予单位】：哈尔滨理工大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN792
【引证文献】
相关硕士学位论文 前3条
1 王海博;一种低功耗高精度Δ-∑调制器的设计[D];云南大学;2016年
2 张道;基于FPGA的土壤数据采集系统[D];西北师范大学;2015年
3 王婷;用于加速度计中的单环四阶∑△调制器设计[D];齐齐哈尔大学;2015年
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