高速TDM-PON系统ONU方案设计与实现
发布时间：2019-06-05 23:59
【摘要】：10G EPON已成为业界公认的目前光接入网提速的主流解决方案之一,要深入的研究10G EPON系统实际应用所面临的各类问题,如深度业务识别、QoS保证等需要基于一个灵活的、可编程设计实现以验证新机制新功能的10GEPON系统平台,而目前商用10GEPON ASIC芯片功能固化,难以满足创新研究的特殊要求,所以设计一款基于FPGA、拥有自主知识产权的10GEPON系统很有必要。此外,随着未来各种网络业务的发展,对接入网络带宽需求势必急剧增加,覆盖范围也将进一步扩大,为满足这些新需求,将单波长速率从10Gbps提升到4OGbps.传输距离扩展到40km的下一代PON系统成为光接入网发展演进的必然趋势之一。本文围绕实现基于FPGA的10G EPON系统平台和满足下一代PON大容量、长距离、广覆盖的目标要求,进行了两款PON系统ONU设备的设计开发,具体开展的工作总结如下： (1)10G EPON ONU电路方案设计、实现 ①参与完成10G EPON ONU总体设计方案：根据需求分析,确立了符合IEEE802.3av国际标准,支持10G上联接口、FE/GE用户接口等技术指标,并进行模块设计。 ②完成电路原理图设计,主要包括PON侧10G接口、FPGA、 SGMII到GMII的接口转换、嵌入式系统等模块电路设计。 ③完成10G EPON ONU单板功能调试及系统联合测试,主要包括PON侧XSBI/SFP+、用户侧FE/GE接口、SGMII to GMII转换等调试及与商用OLT互通、系统联合测试,测试结果表明10G EPON ONU方案符合设计要求。(2)40Gbps TDM-PON ONU电路方案设计、实现 ①参与完成以下行40Gbps,上行10Gbps、分支比1：32,最长传输距离和最大距离差40km为核心目标的TDM-PON ONU总体方案及内部帧过滤复用、40G解帧、相干接收、控制等功能模块设计。 ②完成电路原理图设计,主要包括用户侧10G接口、PON侧40G光模块、FP(GA、时钟、高速XAUI、SFI-5、XFI等的设计。 ③参与电路PCB设计,制定PCB叠层结构、高速接口布线等要求。最终实现的40bps TDM-PON ONU主板多达18层,近24000pins,子板10层,约3000pins。 ④完成单板功能模块的调试,主要包括用户侧接口调试、PON侧接口调试、上行链路及下行链路调试等,调试结果验证了方案设计的合理性和可行性。
[Abstract]:10G EPON has become one of the mainstream solutions to increase the speed of optical access network. In order to deeply study all kinds of problems faced by the practical application of 10G EPON system, such as deep service identification, QoS guarantee and so on, it needs to be based on a flexible. Programmable design and implementation of 10GEPON system platform to verify the new mechanism and new functions, but the current commercial 10GEPON ASIC chip function solidified, it is difficult to meet the special requirements of innovative research, so the design is based on FPGA, It is necessary to have a 10GEPON system with independent intellectual property rights. In addition, with the development of various network services in the future, the demand for access network bandwidth is bound to increase sharply, and the coverage will also be further expanded. In order to meet these new requirements, the single wavelength rate will be increased from 10Gbps to 4OGbPs. The next generation PON system whose transmission distance extends to 40km has become one of the inevitable trends in the development and evolution of optical access network. In this paper, the design and development of two PON system ONU devices are carried out to realize the 10G EPON system platform based on FPGA and to meet the requirements of large capacity, long distance and wide coverage of the next generation PON. The specific work is summarized as follows: (1) 10G EPON ONU circuit scheme design, 1 participate in the completion of 10G EPON ONU overall design scheme: according to the requirement analysis, established in accordance with IEEE802.3av international standards, support 10G uplink interface, FE/GE user interface and other technical indicators, and module design. 2 complete the circuit schematic design, including PON side 10G interface, FPGA, SGMII to GMII interface conversion, embedded system and other module circuit design. (3) complete 10G EPON ONU single board function debugging and system joint test, including PON side XSBI/SFP, user side FE/GE interface, SGMII to GMII conversion debugging, interworking with commercial OLT, system joint test. The test results show that the 10G EPON ONU scheme meets the design requirements. (2) 40Gbps TDM-PON ONU circuit scheme design, 1 participate in the completion of the following lines 40Gbps, uplink 10Gbps, branch ratio 1 鈮，
本文编号：2493911
[Abstract]:10G EPON has become one of the mainstream solutions to increase the speed of optical access network. In order to deeply study all kinds of problems faced by the practical application of 10G EPON system, such as deep service identification, QoS guarantee and so on, it needs to be based on a flexible. Programmable design and implementation of 10GEPON system platform to verify the new mechanism and new functions, but the current commercial 10GEPON ASIC chip function solidified, it is difficult to meet the special requirements of innovative research, so the design is based on FPGA, It is necessary to have a 10GEPON system with independent intellectual property rights. In addition, with the development of various network services in the future, the demand for access network bandwidth is bound to increase sharply, and the coverage will also be further expanded. In order to meet these new requirements, the single wavelength rate will be increased from 10Gbps to 4OGbPs. The next generation PON system whose transmission distance extends to 40km has become one of the inevitable trends in the development and evolution of optical access network. In this paper, the design and development of two PON system ONU devices are carried out to realize the 10G EPON system platform based on FPGA and to meet the requirements of large capacity, long distance and wide coverage of the next generation PON. The specific work is summarized as follows: (1) 10G EPON ONU circuit scheme design, 1 participate in the completion of 10G EPON ONU overall design scheme: according to the requirement analysis, established in accordance with IEEE802.3av international standards, support 10G uplink interface, FE/GE user interface and other technical indicators, and module design. 2 complete the circuit schematic design, including PON side 10G interface, FPGA, SGMII to GMII interface conversion, embedded system and other module circuit design. (3) complete 10G EPON ONU single board function debugging and system joint test, including PON side XSBI/SFP, user side FE/GE interface, SGMII to GMII conversion debugging, interworking with commercial OLT, system joint test. The test results show that the 10G EPON ONU scheme meets the design requirements. (2) 40Gbps TDM-PON ONU circuit scheme design, 1 participate in the completion of the following lines 40Gbps, uplink 10Gbps, branch ratio 1 鈮，
本文编号：2493911
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