图像数字压缩网络相机的设计与实现

发布时间：2018-03-02 08:37

本文关键词： 数字化 JPEG压缩图像传输 FPGA　出处：《大连理工大学》2014年硕士论文　论文类型：学位论文

【摘要】：目前普遍使用的网络视频相机,由于数据传输能力的限制,很难做到高清级。因此图像的前端压缩的需求越来越大,本文根据课题要求设计了图像数字压缩网络相机。方案采用了JPEG压缩标准和UDP通信协议,主要的硬件模块由前端图像采集模块、图像模数转换模块、图像压缩模块、图像网络传输模块和图像接收显示模块组成。其中主控制器本文采用了接口灵活、节约开发成本的XC3S50AN这一款FPGA芯片,图像采集模块采用了CCD传感器,将采集的原始图像数据传输到图像模数转换模块SAA7111芯片,实现图像信号的数字化,再由图像压缩模块ZR36060完成JPEG压缩并经由FPGA传输到图像网络传输芯片W5300,上位机模块则用来接收W5300的数据进行解码、存储和显示。系统的软件部分主要是各模块驱动设计、读写控制设计和上位机显示程序。各模块驱动和读写控制设计是采用Verilog HDL语言编写的,由FPGA根据各模块时序图进行配置,使下位机各模块能正常的工作。其中SAA7111模块是FPGA通过IIC总线对其进行寄存器配置；ZR36060模块则是设计了一个IP核来加载配置参数,其同步时钟信号由SAA7111提供；FPGA作为ZR36060和W5300之间的数据缓存；W5300则只需对其接口和网络参数进行配置以及收发TX/RX存储器大小分配。上位机部分则是采用MFC界面,通过C++编程实现图像的解码、显示和保存等功能。实验结果显示,该系统下位机能够完成对图像的采集、数字化、压缩和网络传输,上位机能够清晰的显示图像。本文所用传感器规格为500×582像素,单帧图像数据量582Kbyte,经ZR36060压缩之后图像大小为29Kbyte,很好的实现了图像数据压缩,压缩比为20：1。
[Abstract]:Because of the limitation of the data transmission ability, it is difficult to achieve high definition level for the network video camera which is widely used at present. Therefore, the demand for the front end compression of the image is increasing. This paper designs the image digital compression network camera according to the requirements of the subject. The scheme adopts JPEG compression standard and UDP communication protocol. The main hardware modules are front-end image acquisition module, image A / D conversion module, image compression module. Image network transmission module and image receiving and displaying module. The main controller adopts XC3S50AN chip, which has flexible interface and saves development cost. CCD sensor is used in image acquisition module. The original image data is transmitted to the image A / D conversion module SAA7111 chip to realize the digitization of the image signal. Then the image compression module ZR36060 completes the JPEG compression and transmits to the image network transmission chip W5300 via FPGA. The upper computer module is used to receive the W5300 data for decoding, storage and display. The software part of the system is mainly about the design of each module driver, read / write control design and host computer display program. Each module driver and read / write control design is written in Verilog HDL language, which is configured by FPGA according to the timing diagram of each module. The SAA7111 module is the FPGA to configure its register through the IIC bus ZR36060 module is designed an IP core to load configuration parameters. The synchronous clock signal is provided by SAA7111 as the data buffer between ZR36060 and W5300. The W5300 only needs to configure its interface and network parameters and allocate the size of TX/RX memory, while the upper computer uses MFC interface. The function of image decoding, displaying and saving is realized by C programming. The experimental results show that the system can collect, digitize, compress and transmit the image clearly, and the upper computer can display the image clearly. The sensor specification is 500 脳 582 pixels. The single frame image data volume is 582 Kbyte.After ZR36060 compression, the image size is 29Kbyte. the image data compression is very good, the compression ratio is 20: 1.
【学位授予单位】：大连理工大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TB852.1

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