集成化可编程遥感图像并行降噪处理机的设计与实现

发布时间：2019-01-03 12:51

【摘要】：CCD图像在其获取过程中由于多种因素的影响会引入一定噪声，这将给后续的图像处理工作带来一定不便，，因此，对其进行降噪处理则显得非常重要。传统的硬件处理方法如DSP和ASIC等在不同程度上具有一定的缺点，对于遥感图像的处理并不能达到理想的效果。专用指令集处理器（ASIP）的出现为解决上述问题提供了一种新的手段，其既具有速度快的优势又具有一定的可编程特性，因此对于本文中遥感大幅图像的并行处理具有良好的适用性。本文依托某实际项目，具体做了以下三个方面工作：首先，结合实际需要设计了本文所用的小波处理算法，并重点介绍了本算法在实际应用中的并行使用方法。其次，设计并实现了一个集成化可编程遥感图像并行降噪处理机。此系统以FPGA为载体，采用基于ASIP的SIMD结构并行阵列处理方式实现大幅图像的分块实时降噪。整个并行处理机主要由ASIP并行处理电路和数据分发与合成电路构成。其可在单片FPGA中集成132个处理内核，集成度高。与传统的SIMD并行处理机不同，此系统中ASIP阵列内部设计有保护性功能单元，使得系统中每个ASIP处理单元具有了一定的指令自主执行能力。最后，通过对上述降噪处理机的结构进行分析，结合实际应用场景，设计了参数配置模块，以便于地面站对其进行工作状态控制和处理参数调整。此外，我们还对运算电路进行了优化，使得处理速度也有一定程度的提高。经过验证，该处理机各项性能及降噪效果达到指标要求。结果表明我们设计的并行降噪处理机是正确有效的。
[Abstract]:In the process of CCD image acquisition, a certain noise will be introduced due to the influence of many factors, which will bring some inconvenience to the subsequent image processing, so it is very important to reduce the noise. The traditional hardware processing methods, such as DSP and ASIC, have some shortcomings in different degrees, and the processing of remote sensing images can not achieve the desired results. The emergence of special instruction set processor (ASIP) provides a new method to solve the above problems. Therefore, it has good applicability for parallel processing of remote sensing large scale images in this paper. Based on a practical project, this paper has done the following three aspects: firstly, the wavelet processing algorithm used in this paper is designed according to the actual needs, and the parallel application method of this algorithm in practical application is introduced. Secondly, an integrated programmable remote sensing image parallel de-noising processor is designed and implemented. The system uses FPGA as carrier and uses SIMD structure parallel array processing method based on ASIP to realize real time noise reduction of large scale image. The whole parallel processor is mainly composed of ASIP parallel processing circuit and data distribution and composite circuit. It can integrate 132 processing kernels in a single chip FPGA with high integration. Different from the traditional SIMD parallel processor, the ASIP array in this system is designed with protective function units, which enables each ASIP processing unit in the system to have the ability to execute instructions autonomously. Finally, by analyzing the structure of the noise reduction processor and combining with the practical application scene, a parameter configuration module is designed to facilitate the ground station to control the working state and adjust the processing parameters. In addition, the operation circuit is optimized to improve the processing speed to a certain extent. It has been proved that the performance and noise reduction effect of the processor meet the requirements. The results show that the parallel noise reduction processor designed by us is correct and effective.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP751

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