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基于FPGA的水声测距系统设计与实现

发布时间:2019-03-01 10:48
【摘要】:水声测距技术是许多声呐系统中非常重要的部分,无论是声学目标的定位、追踪、导航,还是一些水声测量测绘实验等,都离不开高精度的水下距离测量。根据不同的测距应用环境,水声测距对于测量条件、测量精度和测量范围等的要求各不相同。本文主要设计一种用于舰船辐射噪声测量实验的水声测距系统,要求具有较高的测距精度,并且对本身舰船辐射噪声的影响较小。论文根据应用背景,设计并实现了一种基于FPGA的同步钟水声测距系统,主要包括同步发射信标和相关接收机两部分,具有测距精度高、抗干扰性能好、发射效率高、对声场环境影响小的特点。系统的同步通过高稳定度的恒温晶振(OCXO)实现,信标使用PWM调制方式发射宽带脉冲,接收机通过FPGA实现的数字匹配滤波器接收和检测测距脉冲,然后通过SOPC的方式,将时延数据发送给上位机进行距离换算和界面显示。FPGA处理器选用低功耗的Cyclone Ⅲ系列芯片,程序主要由VHDL语言编写,其中用FPGA作DSP运算是其中的难点,而通过SOPC则能使系统的集成度大幅提高。最后通过水池实验对测距系统进行了测试,信标发射的宽带脉冲和接收机匹配滤波器效果都较为理想。实验对近距离测距数据进行了记录和误差分析,结果表明本文设计的同步钟水声测距系统基本符合设计要求。
[Abstract]:Underwater acoustic ranging technology is a very important part of many sonar systems, no matter it is the acoustic target location, tracking, navigation, or some underwater acoustic surveying and mapping experiments, it is inseparable from the high-precision underwater distance measurement. According to different application environments, the requirements of underwater acoustic ranging for measuring conditions, measuring accuracy and measuring range are different. In this paper, a underwater acoustic ranging system for ship radiated noise measurement experiment is designed, which requires high ranging accuracy and has little effect on ship radiated noise. According to the application background, this paper designs and implements a synchronous clock underwater acoustic ranging system based on FPGA. The system mainly includes two parts: synchronous transmitting beacon and correlative receiver. It has high ranging precision, good anti-jamming performance and high transmitting efficiency, and has the advantages of high ranging accuracy, good anti-jamming performance and high transmitting efficiency. The characteristics of small influence on sound field environment. The synchronization of the system is realized by the constant temperature crystal oscillator (OCXO) with high stability. The beacons transmit broadband pulses by means of PWM modulation. The receiver receives and detects the ranging pulses by the digital matched filter realized by FPGA, and then through the SOPC mode. The delay data is sent to the upper computer for distance conversion and interface display. Cyclone 鈪,

本文编号:2432357

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