宽带图像声纳高速浮点信号处理技术研究

发布时间：2019-03-14 07:54

【摘要】：图像声纳是水下目标搜索、定位成像、避险救生、警戒安防等应用领域中的主要探测设备,在国民生产、国家安全领域均发挥着不可替代的作用。随着图像声纳技术和电子信息技术的不断发展,其信号处理方式已由全模拟器件波束形成变为全数字化实时波束形成,其工作体制已逐渐由机械单波束扫描发展为电子多波束成像,工作频率由窄带单频开始向宽频带过渡。随着应用领域和工作环境的不断扩展延伸,图像声纳在设备体积逐渐小型化的同时,对于数字信号处理的动态范围、计算精度等要求也在不断提高。然而由于浮点运算速度相对较慢、计算结构相对复杂,在水声信号处理领域内有关高速大规模浮点处理算法及应用的研究较少见,尤其是在宽带图像声纳中的研究成果就更少。可以预见,随着图像声纳的不断发展,宽带化、浮点化、高速化、小型化已成为其未来必然的技术选择。因此有必要提前展开适合于宽带图像声纳采用的高速浮点信号处理技术研究,以便为未来宽带图像声纳的设计工作提供指导性意见。本文在回顾了窄带图像声纳技术发展、宽带图像声纳定点信号处理研究以及传统浮点信号处理研究的基础上,以高速浮点宽带图像声纳信号处理应用为背景,对多通道浮点脉冲压缩、分布式浮点分数时延滤波和多通道浮点波束形成进行了理论和试验研究。结合匹配滤波理论,分析比较了在DSP及FPGA器件上分别进行单通道时域和频域脉冲压缩的主要性能。针对多通道频域脉冲压缩资源占用大、控制设计复杂难以实际应用的问题,提出了基于片内可编程系统(SOPC)的多通道信号处理框架。利用该框架设计实现了可灵活配置与剪裁的浮点多通道脉冲压缩系统。分析实验了不同工作参数下,该浮点多通道脉冲压缩系统的主主要性能与关键参数。为实现列高精度的时延波束形成,结合分数时延滤波原理,对适合FPGA应用的分数时延滤波器系数设计算法进行了比较。分析了经典的Farrow结构分数时延滤波器,针对其结构复杂、难于浮点化改造的问题,基于分布式算法原理提出了分布式浮点时延滤波器。研究了不同时间优化和空间优化方案下分布式浮点时延滤波器的计算精度、动态范围及资源占用等关键性能。为完成高速浮点波束形成运算,分析了传统浮点乘法器、浮点累加器等运算单元存在的诸多问题。提出了更适于在FPGA上应用的快速移位树、浮点4-2压缩器、分布式浮点累加器等关键运算单元。综合设计了不同构型下的几种多通道浮点波束形成器,通过与分布式浮点时延滤波器相结合,仿真分析了浮点分数时延波束形成器的主要性能。研究了直接扇形地址产生和数据缓存算法,从而对宽带图像声纳数字信号处理结构进行优化、提高整体处理速度。通过对浮点多通道脉冲压缩系统、分布式浮点时延滤波器及多通道浮点波束形成器进行综合,构成了一个宽带图像声纳的浮点信号处理测试系统,通过硬件测试和水池实验对其工作原理及主要性能进行了分析验证。
[Abstract]:Image sonar is the main detection equipment in the application fields of underwater target search, positioning imaging, risk-avoiding life-saving and alert security, and plays an irreplaceable role in the national production and national security field. With the development of the image sonar technology and the electronic information technology, the signal processing method has changed from the full-analog device beam to a full-digital real-time beam forming, and the working system has gradually developed into the electronic multi-beam imaging by the mechanical single-beam scanning, The operating frequency is from the narrow band single frequency to the wide band transition. With the continuous extension of the application field and the working environment, the image sonar is gradually reduced in the volume of the equipment, and the requirements of the dynamic range and the calculation precision of the digital signal processing are also increasing. However, because the operation speed of floating point is relatively slow, the calculation structure is relatively complex, and the research of high-speed large-scale floating point processing algorithm and application in the field of underwater acoustic signal processing is less common, especially in the broadband image sonar. It is foreseen that with the development of the image sonar, the broadband, floating-point, high-speed and miniaturization have become the inevitable choice of technology in the future. Therefore, it is necessary to develop a high-speed floating-point signal processing technique suitable for wide-band image sonar in advance so as to provide guidance for the design of the future broadband image sonar. Based on the review of the technology development of the narrow-band image sonar, the fixed-point signal processing of the broadband image sonar and the traditional floating-point signal processing, the multi-channel floating-point pulse compression is applied to the background of the high-speed floating-point broadband image sonar signal processing application. The theory and experiment of distributed floating point fractional delay filtering and multi-channel floating-point beam forming are studied. In this paper, the main performance of single-channel time-domain and frequency-domain pulse compression on DSP and FPGA is compared. The multi-channel signal processing framework based on on-chip programmable system (SOPC) is proposed in order to solve the problem that the multi-channel frequency-domain pulse compression resource has large occupation and complex control design. And a floating-point multi-channel pulse compression system capable of flexibly configuring and cutting is realized by utilizing the framework design. The main performance and key parameters of the floating-point multi-channel pulse compression system under different working parameters are analyzed. In order to realize the high-precision time-delay wave beam formation, the fractional delay filter coefficient design algorithm for FPGA application is compared with the principle of fractional delay filtering. The classical Farrow structure fractional delay filter is analyzed, and the distributed floating point time delay filter is proposed based on the principle of distributed algorithm. The computational accuracy, dynamic range and resource occupancy of the distributed floating-point time-delay filter under different time-and-space optimization schemes are studied. In order to complete the high-speed floating-point beam forming operation, the problems of the conventional floating-point multiplier and floating-point accumulator are analyzed. The key arithmetic units, such as fast-shift tree, floating-point 4-2 compressor, and distributed floating-point accumulator, which are more suitable for application on FPGA are put forward. In this paper, several multi-channel floating-point beam former in different configurations are designed, and the main performance of the floating-point fractional delay-beam former is analyzed by combining with the distributed floating-point time-delay filter. The direct sector address generation and data caching algorithm is studied, so that the digital signal processing structure of the wideband image sonar is optimized, and the overall processing speed is improved. the floating-point multi-channel pulse compression system, the distributed floating-point delay filter and the multi-channel floating-point beam former are combined to form a floating-point signal processing test system of a broadband image sonar, The working principle and main performance of the system are analyzed and verified by hardware test and pool experiment.
【学位授予单位】：哈尔滨工程大学
【学位级别】：博士
【学位授予年份】：2014
【分类号】：TB56

【相似文献】