无源超高频标签芯片数字部分电路低耗设计与实现

发布时间：2018-01-15 22:03

本文关键词：无源超高频标签芯片数字部分电路低耗设计与实现　出处：《杭州电子科技大学》2015年硕士论文　论文类型：学位论文

【摘要】：射频识别(RFID Radio Frequency Identification)是利用射频信号对目标物体进行非接触式自动识别的技术,已经广泛应用于物流跟踪、身份鉴别、防伪等各行各业。超高频射频识别技术(UHF RFID)具有读写距离远、传送速率快、成本低的优势,越来越引起人们的重视,到2017年将成为我国RFID市场的主流。无源UHF RFID标签芯片的一个关键指标就是功耗,更低功耗的标签芯片性能更加优越,可以在更远的距离上工作。因此,本文重点研究UHF RFID芯片数字基带处理器的低功耗设计,具有一定的工程参考价值。首先,本文介绍CMOS功耗产生的基本原理,并结合超高频电子标签芯片的架构和EPC Class-1 Generation2协议规范,分析了超高频电子标签数字基带电路对功耗的特殊考虑,并总结了常用数字集成电路中采用的低功耗设计方法。其次,提出了一种新颖的数字基带处理器的架构,详细分析了完整的数据通路的流程和各子功能模块的协议要求、实现方法以及仿真的结果。不同于其他设计,本文采用了异步电路设计方法,创新性的提出了三级时序门控思想管理数字基带处理器的工作时序,从顶层模块的划分到具体器件的使用,最大程度上减少了冗余翻转降低了功耗。并在此时序架构基础上,加入了复用、异步计数器、降低模块时钟频率、独热编码计数器、双沿设计的方法进一步优化了功耗。最终在1.8V工艺库下仿真的峰值功耗不超过6.24μW,加入三级门控后的功耗相比之前降低了50%以上。再次,采用Synopsys的EDA工具(Design Compiler,IC Compiler,Prime Time)完成了逻辑综合和后端的物理实现。本文介绍了逻辑综合和后端实现的流程,结合本设计分析了后端低功耗约束脚本的编写,满足了时序的要求和版图的验证。最后,搭建了FPGA验证平台对设计进行了FPGA验证,并在SMIC 0.18μm库下成功流片。本文给出了实物的照片和完整的测试,实测的结果满足协议的要求,整个标签灵敏度为-14.5d Bm。
[Abstract]:RFID Radio Frequency Identification (RFID) is a non-contact automatic identification technology for target objects using radio frequency signals. UHF RFID has been widely used in logistics tracking, identity identification, anti-counterfeiting and other industries. UHF RFID technology has the advantages of long reading and writing distance, fast transmission rate and low cost. By 2017, it will become the mainstream of RFID market in our country. A key index of passive UHF RFID tag chip is power consumption. The lower power consumption tag chip has better performance and can work at a longer distance. Therefore, this paper focuses on the low power design of UHF RFID chip digital baseband processor. It has certain engineering reference value. Firstly, this paper introduces the basic principle of CMOS power generation. Combined with the architecture of UHF tag chip and EPC Class-1 Generation2 protocol specification, the special consideration of power consumption in UHF tag digital baseband circuit is analyzed. The low power design methods used in common digital integrated circuits are summarized. Secondly, a novel architecture of digital baseband processor is proposed. Detailed analysis of the complete data path flow and sub-functional modules of the protocol requirements, implementation methods and simulation results. Different from other designs, this paper uses the asynchronous circuit design method. The idea of three-stage timing gating is proposed to manage the working timing of the digital baseband processor, from the division of the top-level modules to the use of specific devices. On the basis of this timing architecture, multiplexing, asynchronous counter, module clock frequency reduction and single heat coding counter are added. Finally, the peak power consumption in 1.8V process library is less than 6.24 渭 W, and the power consumption after adding three-level gate control is reduced by more than 50%. Again. The EDA tool of Synopsys is used to design the Compiler Compiler. Prime time) has completed the logic synthesis and the back-end physical realization. This paper introduced the logic synthesis and the back-end realization flow, combined with this design has analyzed the back-end low-power constraint script writing. Meet the timing requirements and layout verification. Finally, the FPGA verification platform is built to verify the design of FPGA. In this paper, the physical photographs and complete tests are given. The measured results meet the requirements of the protocol. The sensitivity of the whole label is -14.5 dB 路m.
【学位授予单位】：杭州电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TP391.44;TN402

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