纳米尺度数字电路抗单粒子效应的加固设计方法研究

发布时间：2018-03-25 07:48

本文选题：单粒子翻转　切入点：单粒子瞬态　出处：《合肥工业大学》2016年硕士论文

【摘要】：单粒子效应是引发航天器异常的主要原因。在数字电路中单粒子效应主要包括单粒子翻转(SEU)和单粒子瞬态(SET),前者发生在时序元件中,表现为逻辑状态的翻转；后者发生在组合逻辑和时钟电路中,表现为瞬态脉冲。它们都可能形成软错误,影响电路的可靠性。随着工艺进入纳米尺度,器件尺寸和供电电压不断下降,SEU和SET变得更加严重；而且时钟频率不断上升,组合逻辑中的SET转化为软错误的概率也在增加。因此,如何设计抗SEU和SET的集成电路成为迫切需要解决的问题。本论文研究抗SEU和SET的加固设计方法,旨在提高电路的可靠性。目前,已有的加固设计主要集中在防护SEU和(或)组合逻辑中的SET,不能防护时钟电路中的SET；而且加固成本比较大,影响电路的性能和开销,不利于实际应用。抗SET的方法通常是在组合逻辑末端使用过滤电路,如时间冗余电路、施密特触发器和CVSL门。抗SEU的方法有硬件冗余、分离节点、检错纠错和切断反馈环。同时抗SEU/SET的方法有时间冗余与硬件冗余的结合(如TR-TMR和TR-HLR电路),以及包含延迟单元的锁存器(如FERST和LSEH-1锁存器)。基于SMIC 65nm CMOS工艺,本论文提出一种单粒子加固锁存器设计。该锁存器使用延迟单元和级联C单元构建时间冗余,屏蔽从组合逻辑传播而来的SET。由于采用了嵌入式延迟单元,该锁存器能够容忍时钟信号上的SET。当内部节点受单个粒子轰击而发生逻辑翻转,C单元进入保持状态以避免整个锁存器受影响,抑制SEU。Hspice仿真结果表明,相比已有的加固设计,该锁存器不存在共模故障敏感节点,还能容忍时钟电路中的SET；版图面积、功耗和时钟电路功耗分别平均下降30.58%、44.53%和26.51%；而且该锁存器的功耗对工艺、供电电压和温度的波动不敏感。
[Abstract]:Single particle effect is the main cause of spacecraft anomaly. In digital circuit, single particle effect mainly includes single particle flip (set) and single particle transient set (the former occurs in time series element and is represented as logic state reversal; The latter occurs in combinational logic and clock circuits and is characterized by transient pulses. Both of them may result in soft errors that affect the reliability of the circuit. The device size and the supply voltage are falling. The SEU and SET become more serious; and the clock frequency is rising, and the probability of SET conversion into soft error in combinational logic is also increasing. How to design an integrated circuit that resists SEU and SET becomes an urgent problem to be solved. In this paper, the reinforcement design method of anti-#en2# and SET is studied in order to improve the reliability of the circuit. The existing reinforcement design is mainly focused on the protection of set in SEU and / or combination logic, but not on the set in clock circuit, and the cost of reinforcement is relatively high, which affects the performance and cost of the circuit. The method of resisting SET is to use filter circuits at the end of combinational logic, such as time redundancy circuit, Schmitt flip-flop and CVSL gate. At the same time, the method of resisting SEU/SET includes the combination of time redundancy and hardware redundancy (such as TR-TMR and TR-HLR circuit, and latch containing delay unit, such as FERST and LSEH-1 latch). Based on SMIC 65nm CMOS process, In this paper, a single particle reinforced latch design is proposed. The latch uses delay elements and cascaded C elements to build time redundancy and shield SETs propagating from combinational logic. The latch can tolerate the set on the clock signal. When the internal node is bombarded by a single particle, the logic flip C unit enters the holding state to avoid the whole latch from being affected. The simulation results of suppressing SEU.Hspice show that, compared with the existing reinforcement design, The latch has no common mode fault sensitive node and can tolerate the set in the clock circuit. The layout area, power consumption and clock circuit power consumption are reduced by 30.58% 44.53% and 26.51% respectively, and the power consumption of the latch is insensitive to the fluctuation of technology, supply voltage and temperature.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：V442

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