多核处理器可重构Cache功耗计算方法的研究

发布时间：2018-01-02 16:15

本文关键词：多核处理器可重构Cache功耗计算方法的研究　出处：《计算机科学》2014年S1期 　论文类型：期刊论文

【摘要】：多核动态可重构Cache是解决Cache功耗困扰的一个重要方法。现有Cache功耗模拟器并不能很好地支持多核动态可重构Cache功耗研究,通过对多核动态可重构Cache的功耗模型进行研究,找到了计算可重构Cache的方法和思路,应用CACTI来分别构建各个组成结构的Cache功耗模型,以较为准确地测算可重构Cache的功耗。在Simics模拟器下构建动态可重构Cache,运行测试程序,对比传统的体系结构,可重构Cache的功耗能够得到10.4%的降低。同时,实验中发现功耗的降低不仅仅是动态可重构Cache贡献的,而是由系统综合产生的,因此在低功耗设计中,要综合考虑整体系统的功耗和性能,避免片面地考虑Cache结构而导致整体功耗的提高。
[Abstract]:Multi core dynamic reconfigurable Cache is an important method to solve the problems. The existing Cache power Cache power simulator and reconfigurable Cache power research can not be a good way to support multiple nuclear dynamics, through the research on the power model of multi-core dynamic reconfigurable Cache, find the calculation methods and ideas to reconstruct Cache, using CACTI to construct the Cache model of each power structure respectively, to accurately measure the reconfigurable Cache power consumption. In the Simics simulator to construct dynamic reconfigurable Cache architecture, run the test program, compared with the traditional power, can be reconstructed by the Cache can be reduced 10.4%. At the same time, experiments showed that the reduction in power consumption is not only dynamic the reconstruction of Cache contribution, but by the system, so in the design of low power consumption, power consumption should be considered and the performance of the overall system, avoid one-sided consideration of Cache structure As a result, the overall power consumption is improved.

【作者单位】：北京工业大学计算机学院;
【基金】：国家自然科学基金(61202076) 北京市教委科技计划面上项目(KM201210005022)资助
【分类号】：TP332
【正文快照】： 1引言随着半导体技术的发展,微处理器的新结构与设计层出不穷。在计算机处理器发展过程中性能提高的主要原因得益于时钟周期的缩短,指令访问的局部性原理也使微处理器的性能得到了显著的提高。伴随高性能处理器的快速发展,体系结构功耗问题也愈加显著。时钟频率是性能提高的必

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