闪存的关键电路设计与优化

发布时间：2018-01-02 17:34

本文关键词：闪存的关键电路设计与优化　出处：《山东大学》2014年硕士论文　论文类型：学位论文

【摘要】：近年来,快速闪存凭借优异的性能,在电子信息领域得到了广泛应用。随着信息社会的发展,信息产业正朝着海量信息计算、存储、传输的方向发展。这就要求快速闪存存储技术向大规模、高速度、低功耗、低成本发展。浮栅型存储器的设计,随着工艺特征尺寸的减小而面临着挑战。首先,低供电电压增加了设计难度；第二,随着存储容量的增大,读通路寄生效应更加显著；第三,工艺涨落在所难免。这些问题都与存储器外围电路和读通路的设计密切相关。因此,本文首先深入研究了NOR FLASH工作原理,重点设计了NOR FLASH外围电路,对读通路进行设计、优化,并设计了利用预设Trim值对抗工艺涨落的方法。本文的主要工作和成果如下： 1.深入研究了浮栅晶体管的工作原理,对NOR FLASH的编程、擦除算法进行了详细阐述。 2.设计了几种外围关键电路,包括：(1)两款基准电压源,一款是曲率补偿的高精度基准电压源,另一款是抗工艺涨落的待机状态下的基准电压源；(2)一种瞬态响应增强型VDC电路；(3)改进型电平转换电路。 3.设计优化了读通路关键电路,包括：(1)一种新型的参考电流源电路；(2)电流转电压电路；(3)改进型灵敏放大器。 4.考虑读通路的寄生效应,优化读通路。 5.为了削弱工艺涨落对系统的影响,设计了Trim值读取电路。
[Abstract]:In recent years , the rapid flash memory has been widely used in the field of electronic information . With the development of information society , the information industry is developing in the direction of mass information calculation , storage and transmission . This requires fast flash memory technology to develop in large scale , high speed , low power consumption and low cost . The design of floating gate type memory faces the challenge with the decrease of process feature size . First , the low supply voltage increases the design difficulty ; secondly , with the increase of storage capacity , the parasitic effect of read path is more significant ; thirdly , the process fluctuation is inevitable . Therefore , this paper studies the NOR FLASH working principle , designs and optimizes the read path , and designs the method of using the preset Trim value to counter the process fluctuation . The main work and results of this paper are as follows : 1 . The working principle of floating gate transistor is researched deeply , and the programming and erase algorithm of NOR FLASH is explained in detail . 2 . Several peripheral key circuits are designed , including : ( 1 ) two reference voltage sources , one is the high - precision reference voltage source with curvature compensation , the other is the reference voltage source in the standby state of the anti - process fluctuation ; ( 2 ) the transient response enhanced VDC circuit ; and ( 3 ) the improved level conversion circuit . 3 . The key circuit of read path is optimized , including : ( 1 ) a new reference current source circuit ; ( 2 ) current - to - voltage circuit ; ( 3 ) improved sense amplifier . 4 . Considering the parasitic effect of the read path , the read path is optimized . 5 . Trim value reading circuit is designed to weaken the effect of process fluctuation .

【学位授予单位】：山东大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP333

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