PCIE2.0高速串行总线信号完整性分析

发布时间：2018-01-03 21:41

本文关键词：PCIE2.0高速串行总线信号完整性分析　出处：《内蒙古大学》2014年硕士论文　论文类型：学位论文

更多相关文章： PCIE2.0 S参数 IBIS HSPICE 眼图 SSN

【摘要】：半导体工艺的不断突破带动了新一代高速串行总线的快速发展,PCIE串行总线以其传输速率快,系统拓扑简单等特点,在很多应用领域已经开始取代传统的PCI并行总线,尤其在时序方面进行了简化,但数据速率的增加导致了新问题的出现,为串行总线的信号完整性分析带来了新的挑战。速率达到5Ghz的高速PCIE2.0串行总线在信号完整性分析时要考虑更多的因素,除了传统的反射、串扰外,高速信号带来的介质损耗、趋肤效应、码间串扰和各种寄生参数已不可忽略。本文以Stratix IV GX系列FPGA开发板为模板,以Hspice和HyperLynx为仿真工具,抽取PCIE2.0子卡差分走线的S参数模型,通过背板和连接器搭接完整的数据收发通道,基于IBIS模型和加密Hspice模型分别进行仿真。两种仿真均生成接收端眼图,通过与PCIE2.0协议的眼图模板和时序预算进行比对,在通过6层背板上28inch以内带状线后经过预加重和自适应均衡后的结果完全符合PCIE CEM2.0协议要求,为高速串行信号完整性分析与测试提供了相应的参考依据。同时本文针对3.3V PCIE和12V PCIE电源完整性进行了分析,并利用Hspice对SSN进行建模和仿真,最终得出了片上去耦优于片外去耦的结论。
[Abstract]:Breakthrough semiconductor technology brings the rapid development of a new generation of high-speed serial bus, PCIE serial bus to the transmission speed and characteristics of simple system topology, in many application fields have begun to replace the traditional PCI parallel bus, especially the simplified in time, but the increase of data rate led to the emergence of new problems that brings new challenges for signal integrity analysis of serial bus.
The rate of high speed serial bus PCIE2.0 5Ghz in signal integrity analysis to consider more factors, in addition to the traditional reflection, crosstalk, dielectric loss of high speed signal caused by the skin effect, ISI and various parasitic parameters cannot be ignored. In this paper, the Stratix IV GX series FPGA development board as a template to Hspice and HyperLynx as the simulation tool, extracting PCIE2.0 card S parameters model line, through the data channel backplane and connector complete lap simulation, IBIS model and Hspice model respectively. Based on the encryption of two kinds of simulation results in the formation of the receiving end of the eye, through comparing the eye template and timing budget and PCIE2.0 protocol. In the 6 layer board within 28Inch strip line after the pre emphasis and adaptive equalization after the results are fully consistent with the PCIE agreement of the CEM2.0, for high-speed serial signal integrity analysis and testing The corresponding reference is provided.
Meanwhile, the power integrity of 3.3V PCIE and 12V PCIE is analyzed, and SSN is modeled and simulated by Hspice. Finally, the conclusion that chip coupling is better than off chip decoupling is obtained.

【学位授予单位】：内蒙古大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.6;TP336

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