基于SPARC的嵌入式系统仿真平台研究

发布时间：2018-01-04 12:02

本文关键词：基于SPARC的嵌入式系统仿真平台研究　出处：《大连理工大学》2013年硕士论文　论文类型：学位论文

更多相关文章： SPARC 仿真器 测试用例 排队论 FPGA

【摘要】：目前嵌入式系统己在控制、通信、航空等许多领域得到了普遍应用,嵌入式系统软硬件密切耦合、软件规模、复杂度的急剧上升,嵌入式系统软件测试变得更加困难。几十年来,嵌入式系统仿真器是嵌入式软件测试的高效方法,大大提高了开发效率,降低了测试强度,避免了很大的设计风险。SPARC微处理器的高度可扩展特性,广泛应用于航空航天领域,本文以SPARC架构处理器研究目标,开发基于SPARC的嵌入式系统仿真平台。本文深入研究SPARC的体系结构,实现了一款周期精确的指令集模拟器：基于SPARC的嵌入式系统仿真平台VirtualSPARC. VirtualSPARC在处理器模拟方面,除了包含算术逻辑单元、高速缓存、中断系统等几大模块外,还集成了I2C. UART.键盘、LED等外设仿真单元,支持单步调试、断点调试功能等等。在系统可靠性测试方面,除了采用传统的随机测试、基准测试集测试外,研究了基于FPGA的软硬件协同验证方法与基于马尔科夫使用模型的测试用例生成方法。通过集成测试用例生成模块,模拟外界环境,生成测试用例注入仿真系统各端口,发现并快速定位软件运行时的安全故障,降低了软件开发成本,提高了测试效率。在系统评估方面,研究了基于排队论模型的性能评估方法,通过对嵌入式软件系统建模,抽象出二级串联的排队论模型,利用排队理论对模型分析,可以获得中断丢失率、中断响应时间、系统吞吐量等性能指标与处理器处理能力之间的关系,用以指导嵌入式系统的软硬件设计。通过测试验证,证实本文开发的基于SPARC的嵌入式系统仿真平台VirtualSPARC仿真精确度高,易与扩展,达到了预期效果,其可视化处理器仿真技术以及嵌入式软件动态测试验证方法为处理器芯片设计、嵌入式软件测试等工作提供了一种可控故障的动态测试途径,降低了嵌入式软硬件设计复杂度。
[Abstract]:The embedded system has already been in control, communication, aviation and other many fields has been widely applied to embedded system software and hardware close coupling, the scale of software, a sharp rise in the complexity of the embedded system, software testing becomes more difficult. For decades, the embedded system simulation is an efficient method of embedded software testing, greatly improving the efficiency of development. Reduce the test of strength, avoids the great design risk of.SPARC microprocessor and highly extensible characteristics, widely used in the aerospace field, this paper studies the target processor architecture SPARC, the development of simulation platform of embedded system based on SPARC.
In this paper, the architecture of SPARC is studied deeply, realize a cycle accurate instruction set simulator: VirtualSPARC. VirtualSPARC embedded system simulation platform based on SPARC processor in the simulation, in addition to containing the arithmetic logic unit, cache, several modules interrupt system, also integrates I2C. UART. keyboard, LED and other peripherals to support the simulation unit. Step debugging, breakpoint debugging function and so on. In the aspect of system reliability testing, in addition to the traditional random testing, benchmark test set, the FPGA based software and hardware co verification method and test case generation method based on Markov model. By using the integrated test case generation module, simulation environment, test case generation injection port simulation system, security fault detection and locating software operation, reduce software development cost, improve the measurement The efficiency. In the system of performance evaluation, evaluation method based on queuing theory model, the modeling of embedded software system, abstract queuing model two series, the use of queuing theory to the analysis of the model, can obtain the interrupt loss rate, interrupt response time, the relationship between system throughput and processing capability the design of hardware and software to guide the embedded system.
Through the test, this paper proved that based on the development of the embedded system simulation platform VirtualSPARC simulation accuracy of SPARC is high, and easy to expand, to achieve the desired effect, the visualization processor simulation technology and embedded software dynamic testing method for processor chip design, provides a way of fault controlled dynamic test of embedded software testing work, reduce the the design of the embedded hardware and software complexity.

【学位授予单位】：大连理工大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP368.1;TP391.9

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