串行RapidIO互连系统的设计与实现

发布时间：2018-01-04 23:25

本文关键词：串行RapidIO互连系统的设计与实现　出处：《南京理工大学》2013年硕士论文　论文类型：学位论文

【摘要】：随着无线通信、视频处理和军事等领域对系统带宽的需求持续增长,新型的高速串行互连技术开始逐步取代传统的并行总线。作为新型的高速串行互连技术的一种,串行RapidIO是专门为嵌入式系统而设计的,具有其它互连技术无法比拟的灵活性、稳定性和高效性。本文针对串行RapidIO技术,介绍了目前主流的RapidIO互连系统架构,详细描述了其三层协议规范,即逻辑层、传输层和物理层规范。本文研究了两种RapidIO实现系统互连的方案,并分别从硬件和软件设计两个方面描述具体实现细节。针对成本敏感的通信系统对点对点光纤通信的需求,本文提出了一种基于RapidIO协议的低成本解决方案。以现场可编程门阵列芯片为核心,利用硬件编程、高速收发器以及光模块实现上层逻辑协议、物理层协议和光纤传输。测试结果表明,本方案占用资源少,性能可靠,数据吞吐率达到1.25Gbps,并成功运用于某通信系统中。基于VPX架构的RapidIO互连系统是一种高速、高性能的软件无线电系统,故硬件部分除RapidIO接口设计外还包括高速采样电路设计、DDR3内存接口设计以及时钟和电源设计。现场可编程门阵列串行RapidIO端点利用赛灵思逻辑核实现,数字信号处理器RapidIO端点通过对其加载／存储模块寄存器的操作来实现。
[Abstract]:With wireless communication, video processing and military and other areas of the system bandwidth requirements continue to grow. As one of the new high-speed serial interconnection technologies, serial RapidIO is specially designed for embedded systems. Has the flexibility, the stability and the high efficiency which the other interconnection technology cannot compare. Aiming at the serial RapidIO technology, this paper introduces the current mainstream architecture of RapidIO interconnection system, and describes in detail its three-layer protocol specification, namely the logical layer. Transport layer and physical layer specification. In this paper, two kinds of RapidIO schemes for system interconnection are studied, and the implementation details are described from two aspects of hardware and software design. In order to meet the demand of cost sensitive communication system for point-to-point optical fiber communication, this paper presents a low-cost solution based on RapidIO protocol, with field programmable gate array chip as the core. Using hardware programming, high-speed transceiver and optical module to realize the upper layer logic protocol, physical layer protocol and optical fiber transmission. The test results show that this scheme takes less resources and has reliable performance. The data throughput reaches 1.25 Gbpsand is successfully used in a communication system. The RapidIO interconnect system based on VPX architecture is a kind of high speed and high performance software radio system, so the hardware part includes the high-speed sampling circuit design besides the RapidIO interface design. DDR3 memory interface design and clock and power design. Field Programmable Gate Array Serial RapidIO Endpoint is implemented by using the Syringes Logic Core. Digital signal processor (RapidIO) endpoints are implemented by loading / storing module registers.
【学位授予单位】：南京理工大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TN925;TP368.1

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