一种高速加法器—前置进位加法器研究与设计

发布时间：2018-01-05 02:18

本文关键词：一种高速加法器—前置进位加法器研究与设计　出处：《西南交通大学》2015年硕士论文　论文类型：学位论文

【摘要】：加法器是最基本最常用的算术运算单元,它通常也是限制芯片工作速度的主要因素,高速加法器的设计是必需的。本文采用全定制的方法,进行单元模块电路层次的设计,以及算法层次的优化,以此来提高加法器的速度。虽然全定制设计时间周期较长,但是它设计灵活,能显著提高加法器性能。本文先从加法器的整体算法着手,比较了传统的行波进位算法,和采用进位树的前置进位算法。然后引进前置进位信号(包括进位产生信号,进位消除信号,进位传播信号),并根据点操作原理,采用三种前置进位树(分别是Kogge-Stone树、Han-Carlson树和Brent-Kung树)设计加法器,并对电路速度和面积进行优化。最后对优化后的延迟时间、晶体管数量进行比较,比较结果表明32位Kogge-Stone树形结构的加法器延时最小,晶体管数量最多,32位Brent-Kung树形结构的加法器延时最大,晶体管数量最少,32位Han-Carlson树形结构的加法器延时和晶体管数量在三种进位树中都居中。本文先进行单元模块电路设计,然后搭建三种前置进位树,最后搭建三种树形结构前置进位加法器。单元电路的设计,即进位信号产生电路,进位树单元电路,和求和单元电路,都采用含有静态泄露器的动态电路。在进位树的搭建过程中,使用多米诺逻辑和自定时时钟相结合的方法来减小竞争与冒险,增加时钟的利用率并实现电路功能。在Cadence平台下,用XB0.35um工艺,设计32位高速前置进位加法器。运用仿真工具Spectre对电路仿真并进行功能验证,结果显示32位Han-Carlson树形前置进位加法器,32位Brent-Kung树形前置进位加法器,32位Kogge-Stone树形前置进位加法器优化后的最大延时为6.15ns,6.47ns和5.76ns,分别比最大延时为52.5ns的传统行波进位加法器快了7.54,7.11和8.11倍,完成了高速加法器的设计任务。
[Abstract]:Adder is the most basic and most commonly used arithmetic unit. It is also the main factor that limits the speed of the chip. The design of high-speed adder is necessary. The method of full customization is adopted in this paper. In order to improve the speed of adder, the circuit level of unit module and the optimization of algorithm level are carried out. Although the design time period is long, the design is flexible. It can improve the performance of adder significantly. Firstly, this paper compares the traditional traveling wave carry algorithm with the whole algorithm of adder. And the carry tree precarry algorithm is used. Then the leading carry signal (including carry generation signal, carry cancellation signal, carry propagation signal) is introduced, and according to the principle of point operation. Three kinds of precarried trees (Kogge-Stone tree Han-Carlson tree and Brent-Kung tree) are used to design the adder. The circuit speed and area are optimized. Finally, the delay time and the number of transistors after optimization are compared. The comparison results show that the adder with 32-bit Kogge-Stone tree structure has the minimum delay time. The maximum number of transistors is 32 bit Brent-Kung tree structure with the largest delay and the least number of transistors. The delay of adder and the number of transistors in 32-bit Han-Carlson tree are all centered in the three carry trees. In this paper, the circuit of cell module is designed first, and then three kinds of pre-carry trees are built. Finally, three kinds of tree structure carry adder are built. The design of cell circuit, namely carry signal generation circuit, carry tree unit circuit, and summation unit circuit. In the process of building carry tree, domino logic and self-timing clock are combined to reduce competition and risk. Increase the utilization rate of clock and realize the circuit function. Under the Cadence platform, use XB0.35um technology. The 32-bit high speed carry adder is designed. The circuit is simulated and verified by Spectre. The result shows that the 32-bit Han-Carlson tree is the leading carry adder. The maximum delay of 32-bit Brent-Kung tree forecarry adder is 6.15ns after the optimization of 32-bit Kogge-Stone tree carry adder. 6.47ns and 5.76ns are 7.54 and 8.11 times faster than the traditional traveling wave carry adder with the maximum delay of 52.5ns, respectively. The design task of the high-speed adder is completed.
【学位授予单位】：西南交通大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TP342.2

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