环形栅器件建模研究

发布时间：2018-01-06 12:23

本文关键词：环形栅器件建模研究　出处：《哈尔滨工业大学》2012年硕士论文　论文类型：学位论文

【摘要】：先进集成电路工艺的迅猛发展使得先进集成电路的抗总剂量效应能力也得到一定程度的提升。但是由于工艺、晶圆以及生产线等多方面因素的影响，商用CMOS工艺生产的器件的抗总剂量效应能力差异较大。因此为保证器件在空间辐射环境中的长时间正常工作，仍需采用抗总剂量效应加固技术。本文介绍了总剂量效应的产生机理以及目前较为成熟的总剂量效应加固方法，并采用目前较为常用的环形栅结构设计了容量为8kb的静态随机存取存储器（SRAM）。鉴于目前商用器件的SPICE模型不适合环形栅器件这一问题，本文首先提出了适用于多数环形栅结构的环形栅器件等效宽度提取方法，并对商用SPICE模型中的相关参数提出了相应的调整方法，使目前的商用SPICE模型能够应用于环形栅器件的SPICE仿真。与现存的等效宽长比提取方法的比较结果以及TCAD仿真结果均表明该模型较为准确。为保证本文设计的SRAM的行列译码电路即能采用环形栅结构又能够通过top-down流程实现，，本文研究了SMIC公司0.18μm工艺标准单元建立方法，并设计了三种环形栅标准单元。验证结果表明，本文设计的标准单元能够被数字电路设计工具正确识别并使用。最后采用环形栅结构标准单元结合SMIC0.18μm标准单元库中其他单元本文完成了环形栅结构SRAM的电路版图设计及验证，结果表明本文设计的SRAM子单元能够在10ns的时钟周期下正常工作。
[Abstract]:With the rapid development of advanced integrated circuit technology , the anti - total dose - effect ability of advanced integrated circuit is promoted to a certain extent . However , due to the influence of many factors such as process , wafer and production line , the total dose - effect of devices produced by commercial CMOS technology is different . Therefore , it is necessary to adopt anti - total dose - effect reinforcement technology to ensure the normal operation of the device in space radiation environment . This paper introduces the generation mechanism of total dose effect and the current mature total dose effect reinforcement method , and designs static random access memory ( SRAM ) with capacity of 8 kb using the commonly used ring gate . In view of the problem of unsuitable ring gate devices , the equivalent width extraction method of ring grid devices suitable for most annular gate structures is proposed . The corresponding adjustment methods are proposed for the relevant parameters in the commercial spice model . The current commercial spice model can be applied to the spice simulation of the ring grid device . Compared with the existing equivalent width - length ratio extraction method and the results of the TCAD simulation , the model is more accurate . In order to ensure that the row - column decoding circuit of SRAM designed in this paper can be realized by top - down flow , the design method of 0.18 渭m process standard unit in SMIC is studied , and three kinds of ring gate standard units are designed . The verification results show that the standard cell designed in this paper can be correctly identified and used by the digital circuit design tool . Finally , the design and verification of the circuit layout of the SRAM of the annular gate structure are completed by using the standard cell of the annular gate structure and the other elements in the SMIC 0.18 渭m standard cell bank . The results show that the SRAM subcell designed in this paper can work normally at 10ns clock cycle .

【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333;TN432

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