DDR3 SDRAM控制器的设计和验证

发布时间：2018-01-06 13:08

本文关键词：DDR3 SDRAM控制器的设计和验证　出处：《华南理工大学》2012年硕士论文　论文类型：学位论文

更多相关文章： DDR3 SDRAM CONTROLLER AXI总线 仲裁

【摘要】：相比于上一代存储器，新一代DDR3SDRAM存储器以其容量、性能和功耗等优点被广泛地应用在数字系统领域，，特别是在片上集成系统（SoC）。本文针对提高DDR3SDRAM控制器带宽利用率的策略、扩展多个AMBA总线的MASTER接口、多级仲裁具体应用进行研究。首先，本文基于标准的JEDEC STANDARD DDR3SDRAM SPECIFICATION，提炼出了影响设计功能和性能的重要参数，并设计了严格符合这些参数的时序。根据总体设计框架图，将设计详细划分几个子模块，定义好各个子模块的功能和接口信号整理成设计文档，随后完成了几个子模块的VERILOG HDL硬件语言的描述。其次，在带宽利用率方面，本文提出了：将读写命令间间插激活和关闭命令，充分提高DDR3数据总线利用率。若所有状态机中没有与正在发出的命令同BANK同ROW的操作的命令，则发出最后一个读写命令为WRA/RDA。内部状态机完全流水操作，连续的两个命令完全连续执行。再次，设计了可以扩展多个总线接口的功能，在片上集成系统方面得到了应用。每一个MASTER口都可以根据自身的仲裁优先级对DDR3SDRAM进行数据的读写访问。这个MASTER口以AXI总线进行对接，仲裁的设计采用多级仲裁：TIMEOUT拥有最高优先级，命令的优先级属性具有第二优先级，，AXI总线的端口号具有第三优先级。最后，基于VMM搭建起来的验证平台，对设计的控制器进行了功能验证，所有功能都能满足JEDEC STANDARD DDR3SDRAM SPECIFICATION协议标准，时序正常。成功对DDR3SDRAM存储器进行数据的正常读写。性能上，本设计应用于SoC片上系统上，频率可以跑到800MHz，本文引进的带宽利用率提高方法使得控制器满足SoC的实际需要。
[Abstract]:Compared with the previous generation of memory, the new generation of DDR3SDRAM memory is widely used in the field of digital system because of its capacity, performance and power consumption. This paper aims at improving the bandwidth utilization of DDR3SDRAM controller and extends the MASTER interface of multiple AMBA bus. The concrete application of multilevel arbitration is studied. Firstly, based on the standard JEDEC STANDARD DDR3SDRAM spectrum, this paper abstracts the important parameters that affect the design function and performance. According to the overall design frame diagram, the design is divided into several sub-modules in detail, and the functions and interface signals of each sub-module are defined into design documents. Then the VERILOG HDL hardware language of several sub-modules is described. Secondly, in terms of bandwidth utilization, this paper proposes to activate and close commands between read and write commands. Fully improve the utilization of the DDR3 data bus. If there are no commands in all state machines to operate with BANK and ROW with the commands being issued. Then the last read and write command is issued as WRAP RDA. The internal state machine is completely income operation and two consecutive commands are executed in full succession. Thirdly, the function of extending multiple bus interfaces is designed. Each MASTER port can read and write access to DDR3SDRAM data according to its arbitration priority. This MASTER port uses ax. I bus docking. In the design of arbitration, multilevel arbitration: TIMEOUT has the highest priority, and the priority attribute of the command has the second priority and the port number of the AXI bus has the third priority. Finally, based on the verification platform built by VMM, the function of the controller is verified. All functions can meet the standard of JEDEC STANDARD DDR3SDRAM SPECIFICATION protocol. The timing is normal and the data of DDR3SDRAM memory can be read and written successfully. In performance, this design is applied to the system on SoC chip, and the frequency can run up to 800MHz. In this paper, the improved bandwidth utilization method is introduced to make the controller meet the actual needs of SoC.
【学位授予单位】：华南理工大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TN47;TP333

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