基于FPGA的多片NAND FLASH并行存储控制器的设计与实现

发布时间：2018-01-07 19:43

本文关键词：基于FPGA的多片NAND FLASH并行存储控制器的设计与实现　出处：《山东大学》2012年硕士论文　论文类型：学位论文

【摘要】：随着嵌入式系统的发展,对数据存储量的要求正在快速增长。FLASH具有速度快、密度大、非易失性及可擦除性等特点,正在得到越来越广泛的应用。FLASH主要有NOR和NAND两种,而NAND FLASH具有更小的体积、更快的写入和擦除速度、更多的可擦写次数以及更低廉的每比特价格,成为了大量数据存储的理想器件。基于闪存的固态硬盘,采用FLASH芯片作为存储介质,这也是我们通常所说的SSD。与传统的硬盘相比,它由固态电子存储芯片阵列制成,内部没有机械装置,因此,SSD具有更快的读取速度,没有噪音,发热量低,不会发生机械故障,工作温度范围大,体积小,重量轻,抗震动的优点。虽然有容量小,成本高,数据难以恢复等缺点,但是,随着技术的不断发展进步,固态硬盘的技术发展也将更加完善,固态硬盘也将得到更加广泛的应用。 NAND FLASH的控制逻辑复杂,数据、地址采用同一总线,实现串行读取,随机读取速度慢且不能按字节随机编程。因此,本文探讨了基于Xilinx Spartan-3E的多片NAND FLASH并行存储控制器的设计方案,设计实现了类SRAM接口,处理器能够按照SRAM接口标准对NAND FLASH进行操作而不需要考虑NAND FLASH的接口规范,方便了NAND FLASH应用的扩展。基于FPGA的多片NAND FLASH并行存储控制器,实现了SRAM接口和NAND FLASH接口的转换,将复杂不通用的NAND接口转化为了简单通用的SRAM接口,能够控制多片NAND FLASH的读写等操作；实现ECC校验功能,对写入和读出的数据进行校验操作,提高处理效率；控制多片NAND FLASH芯片,扩大了容量,提高了并行处理能力,便于实现SSD。综上所述,基于FPGA的多片NAND FLASH并行存储控制器的设计实现,不仅具有理论研究的价值,在SSD设计实现方面有实际的利用价值。
[Abstract]:With the development of embedded system, the data storage requirements are the rapid growth of.FLASH high speed, high density, non-volatile and erase characteristics and so on, are getting more and more NOR and NAND two.FLASH mainly used more widely, while NAND FLASH has a smaller volume, faster write and erase speed, more erasing times and more lower price per bit, become the ideal device for large data storage.
The flash based, using FLASH chip as the storage medium, compared to this is what we usually refer to the SSD. and the traditional hard disk, which is composed of solid state electronic memory chip arrays made no mechanical devices, so internal, SSD has faster read speed, no noise, low heat, no mechanical failure, working temperature large range, small size, light weight, anti vibration advantages. Although there is a small capacity, high cost, difficult to restore data shortcomings, however, with the development of technology, technology development of solid state disk will also be more perfect, SSD will be more widely used.
NAND FLASH complex control logic, data address using the same bus, serial read, random read speed is slow and can not be random byte programming. Therefore, this paper discusses the design scheme of Xilinx Spartan-3E multi NAND FLASH parallel storage controller based on the design and implementation of the SRAM interface, the processor can according to SRAM interface standard NAND FLASH to operate without considering the interface specification of NAND FLASH, NAND FLASH for extension of the application.
FPGA multi NAND parallel storage controller based on FLASH, realize the conversion of SRAM interface and NAND FLASH interface, NAND interface complex general SRAM interface into simple and general, can control the multi chip NAND FLASH read and write operations; realize ECC checksum function, check the operation of the data read and write and improve the processing efficiency; control of multi chip NAND FLASH chip, to expand capacity, improve the parallel processing ability to implement SSD.
To sum up, the design and implementation of multi chip NAND FLASH parallel memory controller based on FPGA not only has the value of theoretical research, but also has practical value in SSD design and implementation.

【学位授予单位】：山东大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333;TP273

【参考文献】