一种指令快速完成的ROB退休方案

发布时间：2018-01-12 17:42

本文关键词：一种指令快速完成的ROB退休方案　出处：《计算机工程与应用》2015年24期 　论文类型：期刊论文

【摘要】：针对超标量处理器中长延时的指令长时占用重排序缓存的顶端引起流水线退休缓慢的问题,提出了一种将无异常风险的指令快速退休并将运算结果乱序回写的高效退休机制。该方案将结果缓存器与重排序缓存分离,其中结果缓存器作为运算结果回写的缓存器,重排序缓存负责指令按序退休与精确异常的维护。重排序缓存单元在确认指令不会发生异常后,将指令从重排序缓存中快速退休,结果缓存器继续等待结果并进行乱序回写。实验结果表明,在硬件资源相同的情况下,通过提高重排序缓存器的使用效率,基于该方案的处理器相比于传统的按序退休处理器的性能平均提高33%。
[Abstract]:For long delay instructions in superscalar processors occupying the top of the resort cache causes the problem of slow pipeline retirement. In this paper, an efficient retirement mechanism is proposed, in which the instruction with no abnormal risk can be retired quickly and the results are scrambled back. This scheme separates the result cache from the resort cache. The result buffer acts as the buffer for the write back of the operation results, and the resort cache is responsible for the maintenance of the order retirement and the accurate exception. The resort cache unit verifies that no exception will occur in the instruction. The instruction is retired quickly from the resort cache, and the result buffer continues to wait for the result and write back in disorder. The experimental results show that, under the same hardware resources, the efficiency of the resort buffer can be improved. The performance of the processor based on this scheme is 33% higher than that of the traditional sequential retirement processor.
【作者单位】：浙江大学超大规模集成电路设计研究所;杭州中天微系统公司CPU部门;
【分类号】：TP332
【正文快照】： 1引言在高性能超标量处理器中,基本采用乱序执行方案来获得更好的指令并行度(Instruction-Level Parallelism,ILP)。为了在乱序执行方案中支持精确异常、硬件推测和寄存器重命名等功能,引入了重排序缓存(ReorderBuffer,ROB)机制。在传统方案中,指令解码阶段为每条指令分配ROB,

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