基于FPGA的MAX192控制器仿真设计与研究

发布时间：2018-01-13 18:38

本文关键词：基于FPGA的MAX192控制器仿真设计与研究　出处：《计算机工程与设计》2014年10期 　论文类型：期刊论文

【摘要】：为减轻微处理器频繁控制A/D转换器转换时序与读取A/D转换结果的负担,提出串行A/D转换器MAX192的FPGA控制方法。根据MAX192多通道转换时序的特点,设计基于FPGA的多通道转换控制器和A/D转换结果寄存器阵列。由微控制器指定采样周期、采样点数、采样通道顺序和最大转换通道数等参数来控制FPGA,对MAX192进行转换,且每个采样通道配置1个结果寄存器组,其数量由最大采样通道数决定。仿真结果表明,基于FPGA的MAX192控制器对多通道信号连续转换时,每个通道的平均转换时间与单通道单独转换相比减少了37.5%;结果寄存器可及时存储每次转换结果,便于微处理器及时读取A/D转换结果进行后续快速数字信号处理运算,提高了数据采集系统的实时性,具有工程应用价值。
[Abstract]:In order to reduce the burden of the microprocessor to control the conversion timing of the AP-D converter frequently and to read the AP-D conversion results. A FPGA control method for serial A / D converter (MAX192) is proposed, which is based on the characteristics of MAX192 multi-channel conversion timing. The multi-channel conversion controller based on FPGA and the register array of A / D conversion result are designed. The sampling period and the sampling number are specified by the microcontroller. The sequence of sampling channels and the maximum number of converted channels are used to control FPGA, and each sampling channel is configured with a result register group. The number is determined by the maximum number of sampling channels. The simulation results show that the MAX192 controller based on FPGA converts the multi-channel signals continuously. The average conversion time of each channel is 37.5% less than that of single channel conversion. Results the register can store the results of each conversion in time, which is convenient for microprocessor to read the A- / D conversion results in time for the subsequent fast digital signal processing operation, and improve the real-time performance of the data acquisition system. It has engineering application value.
【作者单位】：常州大学信息科学与工程学院;
【分类号】：TP332
【正文快照】： 0引言MAX192是一款逐次逼近型串行10位AD转换芯片,具有8通道多路转换器、高速转换接口以及高带宽跟踪/保持电路,有超低功耗、可软件配置模拟输入信号极性等特点[1]。传统的A/D控制器设计多以微处理器控制模数转换器,虽然编程简单、控制灵活,但增加了CPU的负担,降低了CPU的工作

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