高性能嵌入式MCU内核设计与功能扩展

发布时间：2018-01-16 18:36

本文关键词：高性能嵌入式MCU内核设计与功能扩展　出处：《华北电力大学》2013年硕士论文　论文类型：学位论文

【摘要】：随着信息技术的发展,作为嵌入式系统的核心,微处理器以其灵活,功能强大等优势,已广泛应用在信息技术的各个领域。无论是家电产品和数字信号处理领域,还是卫星发射导弹制导都离不开微处理器。嵌入式微控制器的典型代表是8051单片机,这种8位(8根数据线,8位指令)的电子器件目前在嵌入式设备中仍然有着极其广泛的应用。微控制器的最大特点是单片化,体积大大减小,从而使功耗和成本下降、可靠性提高。本课题的内容是在研究与理解传统80C51核的基础上,通过引入流水线架构,对程序控制器进行硬布线改造,并扩展外围功能接口,设计实现一款高性能嵌入式MCU HD8051。该MCU芯片内部集成只读存储器(Flash ROM)、随机存储器(RAM)、定时/计数器(Timer/counter)、I/O(input/output)、串行口(UART)、乘累加(MAC)及12C控制器等各种必要功能和外设。本文详细阐述了HD8051单时钟/机器周期的指令流水的实现方式,并对内核中控制单元、算数逻辑运算单元、定时器单元、串口传输单元、端口单元、存储器寄存器控制单元及外围扩展功能接口乘累加器、12C的设计实现均做了详尽的阐述。本文使用verilog语言对各功能单元与外围接口进行RTL描述。在完成设计后,通过modelsim对各功能单元与接口进行仿真验证,仿真结果表明,所设计的MCU的各功能模块的功能时序达到了设计要求,乘累加单元MAC的片内集成使得MCU很好地满足了现今控制领域对高速数字信号的处理的迫切需求,同时12C控制器的引入丰富了MCU的应用领域,通过扩展此类功能接口也很好地体现出单片机向SOC过渡的发展趋势。通过FPGA验证,与传统12个周期的80C51内核比较,在相同时钟频率下单周期指令运行效率为原来的12倍；整个指令集平均运行效率为原来8051的8倍左右,使8051兼容机系列进入了8位高速单片机行列。
[Abstract]:With the development of information technology, as the core of embedded system, microprocessor is flexible and powerful. It has been widely used in all fields of information technology, whether it is home appliances and digital signal processing. The typical representative of embedded microcontroller is 8051 single chip microcomputer, which is 8 bits and 8 data lines. At present, the electronic devices of 8-bit instruction) are still widely used in embedded devices. The biggest characteristic of microcontroller is monolithic and greatly reduced in volume, thus reducing power consumption and cost, and improving reliability. Based on the research and understanding of the traditional 80C51 core, this paper introduces the pipeline architecture to improve the hardware wiring of the program controller and extend the peripheral functional interface. Design and implement a high-performance embedded MCU HD8051.This MCU chip has integrated read-only memory (RAM). Timing / counter / timer / counter / I / O / output / output, serial port / UART. Multiply the accumulator Mac) and 12 C controller and other necessary functions and peripherals. This paper describes the implementation of HD8051 single clock / machine cycle instruction income, and the kernel control unit, arithmetic logic operation unit, timer unit, serial transmission unit, port unit. The memory register control unit and the peripheral extended function interface multiply the accumulator. The design and implementation of 12C are described in detail. This paper uses verilog language to describe each function unit and peripheral interface by RTL. The simulation results of each functional unit and interface by modelsim show that the functional timing of each functional module of the designed MCU meets the design requirements. Intra-chip integration of MAC makes MCU meet the urgent need of high-speed digital signal processing in current control field, and the introduction of 12C controller enriches the application field of MCU. By extending this kind of functional interface, it also reflects the development trend of MCU to SOC. Through the verification of FPGA, it is compared with the traditional 80C51 kernel with 12 cycles. The operation efficiency of the order cycle instruction is 12 times that of the original one at the same clock frequency. The average operating efficiency of the whole instruction set is about 8 times that of the original 8051.
【学位授予单位】：华北电力大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332

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