基于FPGA的闪存数据实时纠错技术的研究

发布时间：2018-01-23 03:56

本文关键词： Flashmemory BCH码 FPGA VerilogHDL　出处：《济南大学》2012年硕士论文　论文类型：学位论文

【摘要】：Flash Memory作为一种使用寿命长、非易失性的存储器，因其读写速度快、在断电的情况下仍能保持所存储的数据信息等优点在存储领域获得了十分普遍的应用。但是，随着Flash Memory制造工艺以及芯片集成度的提高导致其内部的比特错误率也在不断上升，而目前集成于芯片内的通用纠错技术的纠错能力有限，并不能很好满足当前Flash Memory的纠错能力需求。针对以上的问题，作者根据国内外的研究趋势，提出了基于BCH编译码算法的Flash Memory纠错模块(ECC)，并用FPGA芯片进行仿真验证。仿真结果显示并行BCH编码译码器提高了Flash Memory的纠错能力与编码效率。本文的研究内容主要包括以下几个方面： (1)首先介绍了BCH算法的发展历程，BCH码是至今为止所发现的最好的线性分组码之一，适合于对Flash Memory中的随机错误进行纠错。在此基础上，介绍了BCH码的一些相关的代数知识，包括有限域理论、 GF (2m)的构成、有限域的特征和元素的级数以及最小多项式等。在了解BCH码相关知识的基础上，提出BCH码适合于对Flash Memory中的随机错误进行纠错。整个BCH编码码包括编码和译码两个部分，编码过程即通过信息多项式和生成多项式得到校验码多项式，然后得到码字多项式；译码过程首先根据接收码字多项式计算出对应的各个伴随式，接着求出错误位置多项式，最后通过Chien搜索电路求出错误位置完成译码。 (2)从编码效率、纠错能力等方面考虑如何设计BCH码的编译码电路。在BCH编码电路中，限制BCH编码效率的因素主要是数据的传输宽度，由于串行编码电路每个时钟只能处理1bit位的数据，处理效率慢，当码长超过一定长度后，编码器的不能满足Flash Memory纠错的实时需求。在对BCH编码电路的研究基础上，推导出BCH并行编码电路，实现一个时钟可以处理多位数据，提高了数据的处理效率。在BCH译码电路中，同BCH编码电路一样，通过改进伴随式计算电路以及Chien搜索电路，使其从串行改进到并行，提高一个时钟的处理能力，从而提高BCH译码的效率。 (3)使用Verilog HDL语言对BCH编码译码电路进行实现与仿真。首先，使用BCH编码模块对输入到模块中的数据进行编码，由生成多项式生成195比特的校验位，将生成的校验位储存到Flash Memory的SpareArea中；使用BCH译码模块对输入到模块中的码字进行译码，求出15个伴随多项式，并求出错误位置多项式，若发生错误用Chien搜索模块对错误位置多项式进行检索，求出错误位置，根据错误位置对码字中的错误进行纠错。实验结果显示，基于BCH编译码算法的ECC模块纠错能力得到巨大的提高，，达到15bit，并且可以在25MHz的时钟频率正常工作。
[Abstract]:Flash Memory is a kind of memory with long service life and non-volatile, because of its high speed of reading and writing. In the case of power failure can still maintain the stored data information and other advantages in the field of storage has been widely used. With the improvement of Flash Memory manufacturing technology and chip integration, the bit error rate is also increasing, and the error correction ability of the current general error-correction technology integrated into the chip is limited. It can not meet the demand of Flash Memory's error-correcting ability. In view of the above problems, the author according to the research trends at home and abroad. A Flash Memory error correction module based on BCH encoding and decoding algorithm is proposed. The simulation results show that the parallel BCH decoder improves the error-correcting ability and coding efficiency of Flash Memory. The research content of this paper mainly includes the following aspects: Firstly, the development of BCH algorithm is introduced. BCH code is one of the best linear block codes found so far. It is suitable for correcting random errors in Flash Memory. On this basis, some algebraic knowledge of BCH codes is introduced, including finite field theory. On the basis of the knowledge of BCH codes, the composition of GF ~ (2 m), the characteristics of finite fields, the series of elements and the minimum polynomials, etc. It is proposed that BCH code is suitable for correcting random errors in Flash Memory. The whole BCH code consists of two parts: encoding and decoding. In the coding process, the check code polynomial is obtained by the information polynomial and the generating polynomial, and then the codeword polynomial is obtained. In the decoding process, the corresponding accompanying expressions are first calculated according to the received codeword polynomials, and then the misposition polynomials are obtained. Finally, the error position is obtained by the Chien search circuit to complete the decoding. 2) how to design the encoding and decoding circuit of BCH code from the aspects of coding efficiency and error-correcting ability. In the BCH coding circuit, the main factor limiting the efficiency of BCH coding is the data transmission width. Because each clock of serial coding circuit can only handle 1bit data, the processing efficiency is slow, when the code length exceeds a certain length. The encoder can not meet the real-time requirement of Flash Memory error correction. Based on the research of BCH coding circuit, the BCH parallel coding circuit is deduced. The realization of a clock can process multi-bit data and improve the efficiency of data processing. In the BCH decoding circuit, as in the BCH coding circuit, the accompanying computing circuit and the Chien search circuit are improved. It can improve the processing ability of a clock from serial to parallel, so as to improve the efficiency of BCH decoding. 3) implement and emulate the BCH coding and decoding circuit with Verilog HDL language. Firstly, use the BCH coding module to encode the input data into the module. The generating polynomial generates 195 bits of check bits and stores the generated bits in the SpareArea of Flash Memory. The BCH decoding module is used to decode the codewords inputted into the module, and 15 adjoint polynomials are obtained, and the wrong position polynomials are obtained. If an error occurs, the Chien search module is used to retrieve the wrong position polynomial, to find the wrong position, and to correct the error in the codeword according to the wrong position. Experimental results show that the error-correcting capability of ECC module based on BCH coding and decoding algorithm is greatly improved, reaching 15 bits, and can work normally at 25 MHz clock frequency.
【学位授予单位】：济南大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333;TN791

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