基于计算模型的体系结构模拟器研究

发布时间：2018-01-23 04:02

本文关键词： 模拟器计算模型优化　出处：《复旦大学》2013年硕士论文　论文类型：学位论文

【摘要】：随着对处理器性能提升需求的不断增长,如何快速且有效地验证处理器设计的正确性和性能的高效性变得越来越具有挑战性。体系结构模拟器是一种模拟处理器硬件全部或者部分行为的工具软件,并且可以通过简单地修改参数来方便地模拟不同的目标体系结构的行为。因此,模拟器受到了众多处理器设计和体系结构相关领域研究人员的广泛使用。目前使用最为广泛的完全详细模拟的周期精确体系结构模拟器,虽然这样的模拟器可以保证结果的精确性,但是这类模拟器普遍存在开发周期漫长和运行速度缓慢两个方面的问题。现有的绝大多数对周期精确模拟器进行优化的研究工作主要包括对模拟器架构的优化和对模拟器性能的优化,但是这些研究成果都无法同时解决上述的两个问题。另一种类型的模拟器是基于抽象模型的模拟器。这种类型的模拟器的设计思想主要是通过提升模拟器设计模型的抽象层次,即通过计算而非模拟的方式实现模拟器部分或者全部的硬件部件的功能,从而对模拟器的设计和性能进行优化的方式。Interval Simulation就是基于部分抽象模型的设计思路。它的设计假设是只有Miss事件才是对性能结果有重要影响的因素。因此,在模拟过程中,精确模拟造成Miss的事件,而忽略其他非Miss事件的影响。通过只关注造成Miss的事件模拟,达到提升模拟器模拟速度的目标。但是由于需要得到Miss事件的精确结果,对于目标体系结构最终性能结果具有重大影响的一些硬件部件,如高速缓存器等,还是需要基于完全详细模拟的。同时,interval simulation也存在一些精确性方面的问题。由于主要关注Miss事件,而忽略了正常模拟指令流的评估,该模拟器对目标体系结构的最终性能模拟的结果会存在很大的偏差,达到15.62%。本文从更高抽象层次的基于完全抽象模型的角度出发,提出了基于计算模型模拟器的设计思路。这种设计思路首先从目标体系结构中选取出对模拟器模拟的最终性能结果具有重大影响的模块进行相应的计算模型的建立,然后利用这些计算模型计算出每一条指令到达流水线各个阶段的时钟周期——包括取指周期、调度周期、执行周期、完成周期和提交周期,从而获得目标体系结构最终模拟执行的性能结果。这种模拟器的设计思路最大的优势在于完全不需要构建并实现完整的流水线和相关的硬件部件(包括分支预测器和高速缓存器等)进行具体地模拟执行,有利于简化模拟器的设计和提升模拟器的性能。本文的主要贡献包括： (?)分析研究当前主流的周期精确模拟器的设计思路,发现并指出了造成此类模拟器设计结构复杂且运行速度缓慢的主要原因。分析研究interval simulation的设计思路,并指出基于计算模型模拟器与之的不同之处。 (?)提出了基于计算模型模拟器的设计思路,并在此基础上根据对目标体系结构性能结果具有重大影响的因素设计实现三个计算模型,分别为乱序执行流水线计算模型、分支预测错误计算模型和高速缓存失效计算模型。 (?)实验结果表明,基于计算模型模拟器在最终的性能结果的误差率仅为2.47%的情况下,和模拟相同目标体系结构的一款周期精确模拟器的运行速度的加速比达到了22.74倍,并且实际的运行速度达到了1.27MIPS,相比与interval simulation的性能提升了78.19%,并可以支持全系统模拟。
[Abstract]:With the increasing demand of processor performance, efficiency, how to quickly and effectively verify the correctness and performance of processor design is becoming more and more challenging. The architecture simulator is a simulation of the processor hardware all or part of the tool software, and can conveniently simulate different target architectures behavior through simply modify the parameters. Therefore, the simulator has been widely used in many research processor design and architecture.
At present, using cycle accurate Architecture Simulator is the most complete with a wide range of simulation accuracy, although this simulator can guarantee results, but this kind of simulator exists long development cycle and the slow speed of the two aspects of the problem. The most research work to optimize the cycle accurate simulator includes optimization of the simulator architecture and optimization of the simulator's performance, but the results of these studies can also solve the above two problems. Another type of simulator is the abstract model simulator based on design ideas of this type of simulator is mainly through to raise the abstraction level simulator design model, namely by calculation rather than analog way simulator of some or all of the hardware components and function, design and performance of the simulator to optimize the way .Interval Simulation is based on the design part of the abstract model. It is designed to assume only the Miss event is the factors have important influence on the performance of the results. Therefore, in the process of simulation, accurate simulation of the cause of the Miss event, and ignore the other non Miss events. Through the focus on the cause of the Miss event simulation, achieve enhance the speed of the target simulator. But due to the need to obtain accurate results for the Miss event, some hardware components have a great influence on the final performance of the target architecture results, such as cache, still need to complete detailed simulation based on interval simulation. At the same time, there are also some accuracy problems. Because the main concern Miss event. While ignoring the evaluation of normal instruction flow simulation, simulation of the final performance of the simulator to a target architecture, the results will exist deviation, Reach 15.62%.
In this paper, from a higher level of abstraction of the fully abstract model based perspective, put forward a design calculation model based on simulator. The design idea first from the target architecture selected has a significant impact on the final performance of the simulator simulation module, the corresponding calculation model, and then calculate each instruction at each stage of the pipeline clock cycle -- including fetch cycle, using the calculation model of scheduling period, execution cycle, cycle time and deadlines, so as to obtain the performance results of the target architecture. The final simulation execution simulator based on the biggest advantage is that don't need to construct and implement a complete production line and related hardware components (including branch predictor and cache etc.) specific simulation execution, to simplify the design of simulator And improve the performance of the simulator. The main contributions of this article include:
(?) design analysis cycle accurate simulator research current, and points out that the main cause of this kind of simulator design of complex structure and slow speed. Analysis and design approach to interval simulation, and pointed out the difference calculation model and based on the simulator.
(?) the design calculation model based on simulator, design factors based on the structural performance of the target system result has a significant impact on the realization of the three models, respectively, out of order execution pipeline calculation model, branch prediction error calculation model and the cache invalidation model.
(?) the experimental results show that the error model in the simulator performance the final result was only 2.47% cases based on the simulated acceleration and a cycle accurate simulator architecture of the same target speed ratio reached 22.74 times, and the actual operating speed of up to 1.27MIPS, and the performance of interval simulation compared to 78.19% increase, and can support the full system simulation.

【学位授予单位】：复旦大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332

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