快速高稳定性九管SRAM单元电路研究

发布时间：2018-01-24 07:19

本文关键词： SRAM单元九管稳定性静态噪声容限漏电流　出处：《西安电子科技大学》2013年硕士论文　论文类型：学位论文

【摘要】：当前SoC系统中为了提高系统性能都会内嵌各种存储器，，尤其是静态随机存取存储器电路由于兼容标准的CMOS工艺成为嵌入式存储器的首选。这些存储单元不论是在芯片面积还是功耗上都占有非常大的比重，它们的性能决定了整个系统的性能。在SoC系统中设计一块高性能的SRAM电路是至关重要的。传统的六管SRAM存储单元，采用直接存取机理进行读操作。在读操作过程中，数据存储点通过存取晶体管直接与位线相接，由于分压和外部噪声的影响，存储的数据很不稳定。改良型的七管SRAM单元结构特别针对六管SRAM单元读操作破坏问题，采用数据存储点与位线分离的方法，消除了电压分压以及外部噪声的问题，其稳定性得到显著提升。然而，由于只有一个存取NMOS管用于写操作，加上阈值电压损失的作用，其写操作的稳定性及速度不能达到要求。本文研究了一种新型的九管SRAM单元，很好地解决了六管的读操作破坏问题和七管SRAM单元的写操作问题，并且运用HSPICE软件对这几种SRAM单元结构的读操作延时、写操作余量、静态噪声容限、漏电流和动态功耗进行了仿真分析。结果表明九管SRAM单元具有较快的读写速度和更好的稳定性。
[Abstract]:In order to improve the system performance, various kinds of memory are embedded in the current SoC system. In particular, static random access memory circuits have become the first choice for embedded memory due to their compatibility with standard CMOS technology. These memory cells occupy a very large proportion in both chip area and power consumption. Their performance determines the performance of the whole system. It is very important to design a high performance SRAM circuit in SoC system. The traditional six-transistor SRAM memory cell uses direct access mechanism to read. During the read operation, the data storage point is connected directly to the bit line through the access transistor, because of the influence of the partial voltage and the external noise. The data stored is very unstable. The improved seven-tube SRAM cell structure is especially aimed at the destruction of the read operation of the six-tube SRAM unit, and the method of separating the data storage points from the bit line is adopted. The stability of the system is greatly improved by eliminating the problem of voltage partitioning and external noise. However, due to the fact that only one access NMOS tube is used for write operation, the loss of threshold voltage is added. Its write operation stability and speed can not meet the requirements. In this paper, a new type of nine-tube SRAM unit is studied, which can solve the problem of read operation destruction of six tubes and write operation of SRAM unit with seven tubes. And the read delay, write operation allowance and static noise tolerance of these SRAM unit structures are obtained by using HSPICE software. The leakage current and dynamic power consumption are simulated and analyzed. The results show that the nine-transistor SRAM cell has faster read / write speed and better stability.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333

【参考文献】