1GHz X-DSP加法移位单元的设计与实现

发布时间：2018-01-27 12:49

本文关键词： X-DSP ASU运算单元定点运算浮点运算验证综合优化策略　出处：《国防科学技术大学》2013年硕士论文　论文类型：学位论文

【摘要】：数字信号处理器（DSP）是对信号和图像实现实时处理的一类芯片，具有高效率、低功耗和低成本的特点。随着DSP芯片的飞速发展，它在通信、军事、家电等社会生活的各个领域得到了广泛的应用，同时，越来越多的应用对DSP的性能也提出了更高的要求。 X-DSP芯片是一款研制中的32位高性能DSP。该DSP属于自主正向设计，实现多功能定点和浮点运算，拥有极其强大的定点和浮点数值运算能力。它采用超长指令字（VLIW）技术和单指令流多数据流（SIMD）技术，设计目标主频达到1GHz。加法移位单元ASU（AddShift Unit）是X-DSP中定点和浮点运算的主要执行部件之一，本文在深入研究其指令功能的基础之上，设计并实现了该运算单元。主要内容如下：一、从ASU运算单元的总体设计入手，，按照基于标准单元的设计流程对其进行了层次化的设计，同时结合全定制的设计方法，对ASU运算单元的移位关键部件进行了定制设计，达到了整体设计目标。二、深入研究了ASU运算单元的结构，合理地划分了子功能模块，并采用多种方法和设计技巧对各个子功能模块和关键部件进行了逻辑设计，达到了时序的要求。三、对编写好的RTL级代码进行了模拟功能验证，开发了ASU运算单元的测试向量，并结合FPGA的验证方法，对目标设计进行了补充验证，充分保证了ASU运算单元的功能正确性。四、总结了ASU运算单元在逻辑综合时应考虑的一些问题，并针对设计的特点和要求，提出了多种优化策略对目标设计进行优化，通过对不同子模块的多种实现方案进行综合比较，最后选择了合适的方法对ASU运算单元进行设计。最后，在45nm CMOS工艺下，使用Synopsys公司的综合工具（DesignCompiler）在worst case条件下对ASU运算单元进行逻辑综合，时序、面积和功耗方面都获得了比较令人满意的结果：频率达到了1GHz的设计目标，面积为63709.329829平方微米，动态功耗和静态功耗分别为10.5928mW和1.6359mW。
[Abstract]:Digital signal processor (DSP) is a kind of chip for real-time processing of signal and image. It has the characteristics of high efficiency, low power consumption and low cost. With the rapid development of DSP chip, it is in communication and military. Home appliances and other fields of social life have been widely used, at the same time, more and more applications have put forward higher requirements for the performance of DSP. X-DSP chip is a 32-bit high-performance DSP, which belongs to the autonomous forward design and realizes multi-function fixed-point and floating-point operation. It has extremely powerful fixed-point and floating-point value computing capability. It adopts VLIW (very long instruction word) technology and SIMD technology of single instruction stream and multiple data streams. The main frequency of the design is 1 GHz. The additive shift unit (ASU(AddShift) is one of the main execution components of fixed point and floating-point operation in X-DSP. Based on the in-depth study of its instruction function, this paper designs and implements the operation unit. The main contents are as follows: First, starting from the overall design of the ASU operation unit, according to the design process based on the standard unit, the hierarchical design is carried out, and the fully customized design method is combined at the same time. The shift key components of ASU operation unit are customized, and the overall design goal is achieved. Secondly, the structure of ASU operation unit is deeply studied, the sub-function module is divided reasonably, and various sub-function modules and key components are logically designed by various methods and design techniques. Meet the requirements of timing. Thirdly, the simulation function of the RTL code is verified, the test vector of the ASU operation unit is developed, and the target design is supplemented with the verification method of FPGA. The functional correctness of ASU operation unit is fully guaranteed. Fourthly, some problems that should be considered in logic synthesis of ASU operation unit are summarized. According to the characteristics and requirements of the design, various optimization strategies are proposed to optimize the target design. Through the comprehensive comparison of various implementation schemes of different sub-modules, a suitable method is selected to design the ASU operation unit. Finally, in 45nm CMOS process. Using the synthetic tool of Synopsys Company, Design Compiler, under the condition of worst case, the logic synthesis and timing of ASU operation unit are carried out. The results of area and power consumption are satisfactory: the frequency has reached the design target of 1GHz, the area is 63709.329829 square micron. The dynamic and static power consumption are 10.5928mW and 1.6359mW, respectively.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332

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