SRAM的动态故障测试研究

发布时间：2018-01-28 17:37

本文关键词： SRAM 存储器测试动态故障静态故障 TSMC180nm工艺阻抗性开路　出处：《南京航空航天大学》2012年硕士论文　论文类型：学位论文

【摘要】：随着嵌入式存储器在片上系统(SoC)中的使用越来越广泛，嵌入式存储器测试在工业界和学术界受到了广泛关注。随着存储器工艺尺寸的减小，为了获得高存储密度和快速的存取速度，SRAM可能会在制造时出现一些新的缺陷。由于嵌入式存储器通常比较复杂，因此故障的建模和测试成为了一项比较困难的任务。经典的存储器测试算法只适用于静态故障，而不足以测试超深亚微米(Very Deep Sub-Micron, VDSM)技术下出现的新型故障，这类新型故障被称为动态故障。因此，研究SRAM的动态故障具有重要的理论意义与实用价值。本文以SRAM的动态故障测试为研究内容，主要研究内容如下： (1)基于六晶体管构建简化的SRAM电路及其参数的选取。为缩短仿真时间，构建了一种简化的SRAM电路，包括预冲电路和写驱动，并通过仿真证实了此简化电路具有正确的读、写以及保持数据的功能。鉴于本文仿真在TSMC180nm工艺下进行，且结合存储单元的W/L比例限制，最终决定选取了各晶体管的尺寸。 (2) SRAM存储单元的阻抗性开路故障研究。首先介绍了存储单元并对其存在的故障进行了分析研究，重点研究了动态读破坏故障(dRDF)产生的原因及其测试算法，通过仿真实验得出了读操作的次数M、植入故障的阻值和读操作周期之间的联系。然后对静态故障也进行了仿真实验，并比较了静态故障与动态故障之间的差异。 (3) SRAM预冲电路的阻抗性开路故障研究。首先介绍了预充电路并对其存在的故障进行了分析研究，重点研究了未修复写故障(URWF)和未修复读故障(URRF)产生的原因及对应的测试算法，并通过仿真验证了算法的有效性，且发现URWF的测试效率要比URRF的测试效率高。以上所有仿真均采用TSMC180nm工艺，且在动态故障研究中首次采用180nm工艺，最后通过Hspice电路仿真软件进行仿真、验证。
[Abstract]:With the increasing use of embedded memory in SoC (system on Chip), embedded memory testing has attracted wide attention in industry and academia. In order to obtain high storage density and fast access speed, SRAM may have some new defects in manufacturing, because embedded memory is usually more complex. Therefore, fault modeling and testing has become a difficult task. The classical memory test algorithm is only suitable for static fault. But not enough to test the new faults that occur under the very submicron Deep Sub-micron (VDSM) technology, which are called dynamic failures. It is of great theoretical significance and practical value to study the dynamic faults of SRAM. In this paper, the dynamic fault test of SRAM is taken as the research content, the main research contents are as follows: In order to shorten the simulation time, a simplified SRAM circuit is constructed, including pre-punching circuit and write driver. It is proved by simulation that the simplified circuit has the function of reading, writing and keeping data correctly. In view of the fact that the simulation in this paper is carried out under the TSMC180nm technology, and combined with the W / L ratio limitation of the memory cell. The final decision is to choose the size of each transistor. Second, the research of impedance open circuit fault of SRAM memory cell. Firstly, the memory cell is introduced and its faults are analyzed. The cause of dynamic read failure fault and its testing algorithm are studied. The times of read operation M are obtained by simulation experiment. Then the static fault is simulated and the difference between the static fault and the dynamic fault is compared. First, the precharging circuit is introduced and the existing faults are analyzed. The causes of unrepaired write fault (URWFF) and unrepaired read fault (URRFF) and the corresponding test algorithms are studied, and the validity of the algorithm is verified by simulation. The test efficiency of URWF is higher than that of URRF. All of the above simulations are based on TSMC180nm technology, and 180nm process is used for the first time in the dynamic fault research. Finally, the simulation software of Hspice circuit is used to verify the simulation.
【学位授予单位】：南京航空航天大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333

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