阻变存储器电路设计

发布时间：2018-01-29 17:15

本文关键词： 阻变存储器阻变器件模型存储阵列读写方案读写电路设计　出处：《西安电子科技大学》2012年硕士论文　论文类型：学位论文

【摘要】：随着集成电路与半导体加工工艺的不断进步，现有的存储器越来越难以满足电子产品的需求。作为一种新型非易失存储器，阻变存储器以其优越的性能得到了业界的广泛认可。本文首先研究了RRAM器件的基础理论。根据RRAM器件的物理特性，采用两种方法对RRAM器件进行行为建模。其中基于Verilog-A语言的RRAM器件模型成功应用到后续RRAM存储器电路的仿真验证中。其次，本文开展了RRAM器件集成技术研究。设计了基于1R型结构的RRAM存储阵列及其读写方案，理论计算和仿真验证表明，所设计的读写方案能够满足设计要求。最后，在RRAM器件模型和读写方案的基础上，本文基于1.8伏SMIC0.18μm CMOS工艺，，设计了一个存储容量为16×32bit的RRAM存储阵列及外围读写电路（包括译码器，灵敏放大器，电平选择电路，存储阵列，控制电路等），利用Cadence工具对RRAM存储器电路进行了仿真验证。仿真结果表明，RRAM存储器工作正常并能实现数据的准确读写，不存在误读和误写现象。
[Abstract]:With the development of integrated circuit and semiconductor processing technology, the existing memory is more and more difficult to meet the needs of electronic products. As a new type of non-volatile memory. Resistive memory has been widely recognized by the industry for its superior performance. In this paper, the basic theory of RRAM devices is studied firstly. According to the physical characteristics of RRAM devices. Two methods are used to model the behavior of RRAM devices. The RRAM device model based on Verilog-A language is successfully applied to the simulation of subsequent RRAM memory circuits. Secondly. In this paper, the integrated technology of RRAM devices is studied. The RRAM memory array based on 1R structure and its reading and writing scheme are designed. The theoretical calculation and simulation results show that. The designed reading and writing scheme can meet the design requirements. Finally, based on the RRAM device model and read and write scheme, this paper based on 1.8 V SMIC0.18 渭 m CMOS process. A 16 脳 32bit RRAM memory array and peripheral read-write circuits (including decoder, sensitive amplifier, level selection circuit, memory array, control circuit, etc.) are designed. The simulation results show that the RRAM memory works well and can read and write the data accurately without misreading and miswriting.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333

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