基于编译实现微线程的故障检测机制关键技术研究

发布时间：2018-02-02 19:43

本文关键词： 微线程寄存器窗口 RTL 故障注入　出处：《哈尔滨工业大学》2012年硕士论文　论文类型：学位论文

【摘要】：近年来，随着容错技术的发展，软件容错技术作为一种提高软件可靠性的重要方法越来越引起关注。软件容错的主要技术包括：基于重复指令的错误检测技术（EDDI），基于数字签名的控制流检测(CFCSS)技术和源到源编译容错等。它们在编译阶段的不同抽象层次对软件进行加固，生成具有容错性能的应用程序。本文提出的微线程故障检测方法也是一种基于编译的容错，它是在编译阶段的中间语言RTL上进行，并在SAM模拟器上进行故障注入实验。首先，本文对处理器核内故障容错方法研究近况进行分析，，比较其差异。然后深入研究了UltraSPARC T2平台，包含架构的特点，处理器架构，指令集和traps等方面的内容。重点是寄存器窗口的相关内容，包括寄存器窗口的原理和相关的指令。接着，本文描述了微线程故障检测方案的算法思想和整体设计方案。微线程故障检测方案可以概括为结合UltraSPARC T2平台的，在编译器的中间表示层RTL级别实现的一种全指令复制规则的容错方案。这种方案既不依赖于前端特定的高级语言，也不依赖于后端的目标平台，因此具有很强的适应性。最后，本文对微线程方案进行详细设计。这部分首先研究了GCC编译相关技术。深入剖析了GCC编译过程，重点是从中间表示Gimple Tree到RTL的生成过程，以及RTL优化和处理过程，汇编代码输出过程。其次，本文从简单的赋值表达式，算术逻辑运算表达式，特殊的表达式和函数调用等几种指令类型的处理过程对微线程的具体实现进行描述。再次，利用故障注入平台针对我们的微线程故障检测方案进行故障注入实验，并对实验结果进行分析。从实验结果可以看出，本文提出的基于编译的微线程故障检测技术在容错性能上有较好的表现，并且牺牲的时间和空间代价也在合理的范围内。
[Abstract]:In recent years, with the development of fault-tolerant technology. As an important method to improve software reliability, software fault-tolerant technology has attracted more and more attention. The main techniques of software fault tolerance include: error detection based on repeated instructions (EDDI). Control flow Detection (CFCSS) technology based on digital signature and source-to-source compilation fault tolerance are used to reinforce the software at different abstract levels in the compilation stage to generate applications with fault-tolerant performance. The fault detection method proposed in this paper is also a fault tolerance based on compilation. It is implemented on the intermediate language RTL in the compilation stage and the fault injection experiment is carried out on the SAM simulator. Firstly, this paper analyzes the research status of fault tolerance method in processor core and compares its differences. Then, the paper deeply studies the UltraSPARC T2 platform, including the characteristics of architecture and processor architecture. Instruction set and traps. The emphasis is on the register window, including the principle of register window and related instructions. Then, this paper describes the algorithm and the overall design of the micro-thread fault detection scheme, which can be summarized as a combination of UltraSPARC T2 platform. A fault-tolerant scheme for full instruction replication rules implemented at the RTL level in the intermediate presentation layer of the compiler, which does not depend on either the front-end specific high-level language or the back-end target platform. Therefore, it has strong adaptability. Finally, this paper designs the scheme of tasklets in detail. In this part, the related techniques of GCC compilation are studied, and the process of GCC compilation is deeply analyzed. The emphasis is on the generation process from intermediate representation of Gimple Tree to RTL, as well as the RTL optimization and processing process, and the assembly code output process. Secondly, this article starts with simple assignment expressions. Arithmetic and logic operation expressions, special expressions and function calls and other instruction types of the processing process to describe the specific implementation of the tasklet. Again. The fault injection experiment is carried out on our micro-thread fault detection scheme by using the fault injection platform, and the experimental results are analyzed, which can be seen from the experimental results. The compile-based micro-thread fault detection technique presented in this paper has a good performance in fault-tolerant performance, and the cost of sacrificing time and space is within a reasonable range.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP302.8

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