一种用于DSP的乘法器设计

发布时间：2018-02-23 20:32

本文关键词： 16×16乘法器优化Booth算法传输门符号位优化　出处：《沈阳工业大学》2012年硕士论文　论文类型：学位论文

【摘要】：随着图像采集，语音识别等数字信号处理在社会生活中应用的越来越广泛，数字信号处理器（DSP）在社会生活中发挥的作用越来越重要。手机，电视甚至高档汽车上都不能缺少DSP的身影。工艺的进步和技术的成熟，使DSP能在保持高性能的同时，价格越来越低廉，稳定性越来越好。这使得DSP在工业控制领域被广泛应用。对于DSP来说乘法是其核心的运算，所以一个乘法器性能的优劣，可以直接影响DSP的性能。在设计乘法器的时候，我们要根据需求综合考虑设计时间，工作速度，芯片面积，产品功耗等各个方面的因素，对各种方案进行取舍。本文设计的是一个用于工业控制领域的DSP中的乘法器模块，，在研究了乘法器的各种实现方法后，发现采用全定制方法设计的基于优化Booth算法的阵列乘法器是一种很好的方案。本文首先介绍了乘法器的基本原理，以及生成部分积和压缩部分积的几种方法，其中推导了Booth算法和优化Booth算法，并详细分析优化Booth算法的好处。由于采用优化Booth算法是对乘数的偶数位及相邻两位进行交替编码产生部分积，因此可以将部分积的数目减少一半。在部分积压缩部分对符号位产生提出了一种优化方法算法。分别对有符号和无符号的情况进行具体讨论。在具体的电路实现上，大量采用了传输门和传输管来实现逻辑功能，这样的好处是大大节省芯片面积。本文采用Chart0.35um BiCmos工艺，分别半定制设计和全定制设计了一个可选择有符号数乘法或者无符号数乘法的16×16乘法器。通过Modelsim验证乘法器逻辑功能的正确性。全定制乘法器的面积是218842.72um~2，半定制乘法器的面积为328764um2。全定制乘法器的最坏情况延迟为8ns。
[Abstract]:With the increasing application of digital signal processing such as image acquisition and speech recognition in social life, digital signal processor (DSP) plays a more and more important role in social life. DSP can not be absent on TV or even high-end cars. With the progress of technology and maturity of technology, DSP can keep its high performance while the price becomes cheaper and cheaper. Stability is getting better and better. This makes DSP widely used in the field of industrial control. Multiplication is its core operation for DSP, so the performance of a multiplier can directly affect the performance of DSP. We should consider the design time, the working speed, the chip area, the product power consumption and so on according to the demand synthetically consider the design time, the chip area, the product power consumption and so on each aspect factor, carries on the choice to each kind of plan. This paper designs a multiplier module in the DSP which is used in the industrial control field. After studying the various implementation methods of the multiplier, it is found that the array multiplier based on the optimized Booth algorithm is a good scheme. This paper first introduces the basic principle of multiplier and several methods of generating partial product and compressed partial product. Among them, Booth algorithm and optimized Booth algorithm are derived. The advantage of optimized Booth algorithm is analyzed in detail. Because the optimal Booth algorithm is used to produce partial product by alternating coding the even bits and adjacent bits of multipliers. Therefore, the number of partial product can be reduced by half. In the partial product compression part, an optimization algorithm for symbol bit generation is proposed. The signed and unsigned cases are discussed in detail. A large number of transmission gates and transfer tubes are used to achieve logic functions, which greatly saves the chip area. In this paper, Chart0.35um BiCmos process is used. In this paper, a 16 脳 16 multiplier which can select signed number multiplication or unsigned number multiplication is designed, respectively. The logical function of multiplier is verified by Modelsim. The area of full custom multiplier is 218842.72um2 and semi-custom multiplier is 218842.72um2. The area of multiplier is 328764um2.The worst-case delay of fully customized multiplier is 8ns.
【学位授予单位】：沈阳工业大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332.22

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