基于CoreConnect总线的SDRAM控制器设计与验证

发布时间：2018-02-24 00:37

本文关键词： PLB总线 DCR总线 SDRAM存储器 SDRAM控制器　出处：《西安电子科技大学》2015年硕士论文　论文类型：学位论文

【摘要】：随着现代社会进入了信息化时代,各种各样的信息都得以快速发展,伴随而来的是数据的存储量越来越大,所以对存储芯片的要求也越来越高。大容量、高安全性的高速存储芯片已成为了时代发展的主流。SDRAM(Synchronous Dynamic Random Access Memory,同步动态随机存储器)凭借其集成度高、功耗低、可靠性高、处理能力强等优势成为最佳选择。但是SDRAM却具有复杂的时序,为了使其满足日益增长的存储需求,SDRAM存储器的控制芯片应运而生。虽然SDRAM控制器已经发展到了DDR4(Double-Data-Rate Fourth Generation Synchronous Dynamic Random Access Memory,双倍速率的第四代同步动态随机存储器),但其设计复杂,成本较高。本文设计的SDRAM控制器正是为了解决这个问题。本文选择可编程逻辑器件中广泛使用的FPGA(Field-Programmable Gate Array,现场可编程门阵列),使用硬件描述语言Verilog,遵循自顶向下的设计思想实现对SDRAM控制器的设计。本文分析了SDRAM控制器的发展现状,确认其设计目标。通过分析CoreConnect总线中的PLB(Processor Local Bus,处理器局部总线)总线协议、DCR(Device Control Register Bus,设备控制寄存器总线)总线协议,以及SDRAM存储器的性能、特点、时序要求,设计出SDRAM控制器的各项性能指标、所需实现功能以及其时序要求。随后,对SDRAM控制器的各个模块进行详细设计。因PLB总线时序和SDRAM存储器的时序不同,故在接口转换单元采用大量异步FIFO(First Input First Output,先入先出队列)进行跨时钟域处理;在数据控制模块后设计了校验和错误检测模块,采取ECC校验和奇偶校验两种检验方式保证数据存储的安全性;采用片选空间的起始、结束地址可编程,SDRAM的行列、逻辑Bank可编程的设计方法提高本设计的适用范围。最后采用模块级验证和系统级验证两种方法对SDRAM控制器进行验证,通过对波形图的分析,本设计能够实现从PLB总线发送单拍、四字Line、八字Line、双字Burst、四字Burst操作到SDRAM存储器。通过大量的验证数据可得出结论:本文所设计的SDRAM控制器实现了从PLB总线向SDRAM存储器发送数据的基本功能。本设计的成本低、设计简单、占用资源少,其设计原理适用于同类SDRAM控制器,以及低成本的大容量存储器。
[Abstract]:With the modern society has entered the information age, all kinds of information have been developed rapidly, accompanied by more and more data storage, so the demand for memory chips is also getting higher and higher. High-security high-speed memory chip has become the mainstream of the times. SDRAMN synchronous Dynamic Random Access memory (synchronous dynamic random access memory) has high integration, low power consumption and high reliability. Such advantages as strong processing power are the best choice. But SDRAM has complex timing, In order to satisfy the increasing storage demand, the control chip of SDRAM memory has come into being. Although the SDRAM controller has been developed to DDR4(Double-Data-Rate Fourth Generation Synchronous Dynamic Random Access memory, and 4th generation synchronous dynamic random access memory with double rate, its design is complicated. The SDRAM controller designed in this paper is designed to solve this problem. This paper selects FPGA(Field-Programmable Gate Array, a field programmable gate array, which is widely used in programmable logic devices, and uses the hardware description language Verilog, following the top-down. In this paper, the development of SDRAM controller is analyzed, and the development of SDRAM controller is analyzed. By analyzing the PLB(Processor Local bus (PLB(Processor Local bus) bus protocol in the CoreConnect bus, the device control register bus bus protocol, and the performance, characteristics and timing requirements of the SDRAM memory, The performance indexes, functions and timing requirements of SDRAM controller are designed. Then, the modules of SDRAM controller are designed in detail. Because the timing of PLB bus is different from that of SDRAM memory, Therefore, a large number of asynchronous FIFO(First Input First output and first-in first-out queue are used in the interface conversion unit to process across the clock domain, and the checksum error detection module is designed after the data control module. Using ECC check and parity check to ensure the security of data storage, using the start of chip selection space, end address programmable SDRAM column, The logical Bank programmable design method improves the scope of application of the design. Finally, the SDRAM controller is verified by module level verification and system level verification. By analyzing the waveform diagram, the design can send a single beat from the PLB bus. Four word line, eight word line, two word burst, four word Burst operate to SDRAM memory. Through a lot of verification data, we can draw a conclusion: the SDRAM controller designed in this paper realizes the basic function of sending data from PLB bus to SDRAM memory. Its design principle is suitable for similar SDRAM controller and low cost mass memory.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TP333

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