可配置EDGE处理器执行单元的分析与设计

发布时间：2018-02-24 07:14

本文关键词： 可配置 EDGE处理器体系结构执行单元　出处：《哈尔滨工业大学》2013年硕士论文　论文类型：学位论文

【摘要】：随着人们对处理器各方面的要求越来越高，传统的超标量处理器因发展受阻而难以为继，分片式处理器结构应运而生，具有块原子性、显式通信等特点的EDGE（Explicit Data Graph Execution）指令集体系结构因为适应分片式处理器而得到广泛应用，采用EDGE指令集体系结构、具有可配置功能的的处理器被称为可配置EDGE处理器，其中，可配置功能是指EDGE处理器能够根据程序或线程的不同而采用不同的物理核数构成逻辑核对其进行处理，所以可配置EDGE处理器具有更高的灵活性、适应性，从而也成为国内外研究热点；由于执行单元是处理器中举足轻重的一环，本文主要针对可配置EDGE处理器的执行单元进行了详细的研究与设计。经典标量、超标量处理器的执行单元通常只包含简单的算术逻辑单元、保留站等结构；EDGE处理器的执行单元除了包含算术逻辑单元外，还包含支持块原子性特点的指令缓冲、状态缓冲、操作数缓冲等结构，以及支持显示通信特点的相应功能结构；可配置EDGE处理器的执行单元除了包含一个特有的支持可配置功能的可配置机制外，它的指令缓冲、状态缓冲、操作数缓冲、算术逻辑单元等结构在数目上与EDGE处理器的执行单元也有区别。可配置EDGE处理器执行单元的可配置机制调整出执行当前程序最合理的物理核数，指令缓冲、状态缓冲、操作数缓冲均包含128个缓冲槽，刚好容纳一个指令块译码后的相应信息，inst_select（指令选择）结构选择出指令块中能够执行的优先级最高的一条指令，这条指令被称为definite指令，，inst_read（指令读取）结构从definite指令、两条bypass（旁路）指令中选择出能够执行的优先级的最高一条指令，算数逻辑单元计算出最终选出的一条指令的结果。对设计的可配置EDGE处理器执行单元的具体结构进行了verilog实现、modelsim功能仿真和design compiler综合后，结果表明，所设计的可配置EDGE处理器执行单的具体结构功能正确，能够针对目前资源利用率的情况调整执行程序的物理核数，能够执行一个指令块中优先级最高的一条指令，能够硬件实现，采用smic18工艺库时，能够在235Mhz的频率下工作。
[Abstract]:With the increasing demands on the processors, the traditional superscalar processors are difficult to continue because of the development of the traditional superscalar processors, and the chip processor architecture emerges as the times require, and it has block atomicity. The EDGE(Explicit Data Graph execution) instruction set architecture with the characteristics of explicit communication is widely used because it adapts to the chip processor. The processor with configurable function is called the configurable EDGE processor, which adopts the EDGE instruction set architecture. Configurable function means that the EDGE processor can be processed by using different physical kernel numbers according to the program or thread, so the configurable EDGE processor has higher flexibility and adaptability. Therefore, it has also become a research hotspot at home and abroad. As the execution unit is an important part of the processor, this paper mainly focuses on the detailed research and design of the execution unit of the configurable EDGE processor. The execution unit of a classical scalar processor usually contains only simple arithmetic logic units. In addition to arithmetic logic units, the execution units of edge processors with reserving stations also contain instruction buffers that support the atomicity of blocks. The execution unit of the configurable EDGE processor, in addition to a configurable mechanism supporting configurable functions, provides instruction buffering. The number of state buffers, operands buffers and arithmetic and logic units are different from those of EDGE processors. The configurable mechanism of the configurable EDGE processor execution unit adjusts the most reasonable number of physical cores, instruction buffers, state buffers and operands buffers for executing the current program, all of which contain 128 buffers. The instruction selection structure selects the highest priority instruction that can be executed in the instruction block. This instruction is called the definite instruction. In two Bypass-by-pass instructions, the highest priority instruction can be executed, and the arithmetic logic unit calculates the result of the final selected instruction. The concrete structure of the configurable EDGE processor execution unit is simulated by verilog and synthesized with design compiler. The results show that the concrete structure function of the configurable EDGE processor execution unit is correct. It can adjust the number of physical kernel of executing program according to the current resource utilization, can execute one instruction with the highest priority in an instruction block, can be realized by hardware, and can work at the frequency of 235MHz when using smic18 process library.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332

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