RRAM及其在FPGA设计中的应用研究

发布时间：2018-03-03 13:29

本文选题：RRAM　切入点：FPGA　出处：《复旦大学》2013年硕士论文　论文类型：学位论文

【摘要】：由于现场可编程逻辑门阵列(FPGA)具有灵活可编程性、设计周期短、成本低等优点,广泛应用于消费电子、通信设备以及航空电子等领域。但传统的SRAM型FPGA掉电信息丢失,在增加板级硬件开销的同时也带来了系统可靠性与数据安全性问题。而反熔丝型和Flash型FPGA虽然具有非易失性,但其CMOS工艺兼容性差、编程电压高。针对SRAM、反熔丝和Flash型FPGA器件的不足,本文研究了新型阻变存储器RRAM在FPGA设计中的两个关键问题：RRAM数学模型和RSRAM编程点电路设计。 RRAM的数学模型是RRAM应用推广的关键因素之一。本文采用分离变量法的思想,使用复数来构造RRAM数学模型。首先,使用复数阻抗将四种基本元器件电阻、电容、电感和忆阻器memristor统一到广义欧姆定律。然后分析了memristor复阻抗模型中的模值(即阻抗大小)与相位的物理来源,用线性迁移模型[3,4]来阐释复阻抗大小的物理来源,用势垒跃迁模型[3,4]来表征复阻抗相位的物理来源,并给出了仿真结果。针对传统SRAM型FPGA和Flash型FPGA所存在的不足,设计了兼具两者优点的FPGA编程点电路。采用2组2T1R(two transistors and one memristor)型RRAM编程配置电路与6管SRAM电路相结合,构成10T2R(ten transistors and two memristors)型RSRAM编程点电路。10T2R型RSRAM结构具有非易失性、CMOS工艺兼容性好、RRAM对SRAM电路干扰小、且支持高速在线编程和非易失离线编程两种模式等特点。仿真表明：高速在线编程方式时,读写延时不超过50ps；非易失离线编程方式时,上电载入延时不超过200ps。基于10T2R型RSRAM单元电路设计了RSRAM存储阵列电路,采用经典的存储器架构,由32行32列10T2R型RSRAM单元电路、行列译码电路和读写驱动电路构成。仿真表明,该RSRAM存储阵列电路能够正常完成数据读写与上电数据载入,且延时不超过2ns。最后给出了版图设计。
[Abstract]:Due to the advantages of flexible programmable logic gate array (FPGA), short design period and low cost, it is widely used in consumer electronics, communication equipment and avionics, but the traditional SRAM type FPGA power loss information is lost. At the same time, the system reliability and data security problems are brought about by increasing the hardware overhead of board level. Although anti-fuse type and Flash type FPGA are non-volatile, their CMOS process compatibility is poor. The programming voltage is high. In view of the shortcomings of SRAM, anti-fuse and Flash type FPGA devices, two key problems in FPGA design of new resistive memory RRAM are studied in this paper: the mathematical model of RRAM and the design of RSRAM programming point circuit. The mathematical model of RRAM is one of the key factors in the application and popularization of RRAM. In this paper, the mathematical model of RRAM is constructed by using the idea of separating variables and using the complex number. The inductor and resistor memristor are unified into the generalized Ohm law. Then, the physical source of the mode value (i.e. impedance magnitude) and phase in the memristor complex impedance model is analyzed, and the physical source of the complex impedance size is explained by the linear migration model [3 / 4]. The physical source of the complex impedance phase is characterized by the barrier transition model [3H4], and the simulation results are given. In view of the shortcomings of traditional SRAM FPGA and Flash FPGA, a FPGA programming point circuit with both advantages is designed. Two sets of RRAM programming configuration circuits of 2T1RX two transistors and one memory storr are combined with 6 transistor SRAM circuits. The 10T2R transistors and two memristorsType RSRAM programming point circuit .10T2R RSRAM structure has good compatibility with non-volatile CMOS process. RRAM has less interference to SRAM circuit. The simulation results show that the read / write delay is less than 50 pss in high speed online programming mode, and the load delay is not more than 200ps in non-volatile off-line programming mode. Based on 10T2R type RSRAM cell circuit, the RSRAM memory array circuit is designed, which is composed of 32 lines of 32-column 10T2R type RSRAM cell circuit, column decoding circuit and read-write drive circuit. The RSRAM memory array circuit can complete data reading and writing and power on data loading normally, and the delay is not more than 2ns. Finally, the layout design is given.
【学位授予单位】：复旦大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333;TN791

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