I-CASH中数据页压缩的SOPC实现

发布时间：2018-03-04 17:06

本文选题：混合存储　切入点：现场可编程门阵列　出处：《华中科技大学》2013年硕士论文　论文类型：学位论文

【摘要】：固态盘（SolidStateDisk，SSD）存储技术最近几年飞速发展，凭借其优异的性能占领了部分市场。但SSD在寿命和成本上仍然与硬盘（HardwareDiskDrive，HDD）有比较大的差距。因此，在消费类市场中SSD的高成本使其无法普及，而在企业应用中其可靠性又不足。另一方面，HDD已经越来越不能满足系统对I/O的高速请求。因此，出现了利用SSD和HDD这两种存储技术优势而将其结合的混合存储技术。通过使用这种混合存储技术希望得到接近于SSD的性能而具有HDD的大容量并延长系统整体寿命。 I-CASH（IntelligentlyCoupledArrayofSSDandHDD）则是一种将SSD和HDD并列使用的混合存储系统。I-CASH利用了数据的内容局部性原理，将不常改变的参考页数据存入SSD中，而只将各数据页相对于参考页数据不同的差异数据存入HDD中。这样相对于HDD来说实现了数据压缩的功能，从而系统可以获得若干倍HDD的性能；另外由于减少了对SSD的写操作，因此系统也可以获得比SSD更长的寿命。对于I-CASH的结构设计，使用了SOC主控芯片实现方案，该方案由主控芯片内部的专用硬件电路完成最主要的数据计算，芯片内部的CPU则只负责较简单的数据管理；在对I-CASH系统的实现方面，由于方案整体的复杂性，仅对上述方案中涉及的I-CASH页压缩子系统的设计及其在FPGA上的实现进行了深入研究，给出了页压缩子系统的结构，介绍了它的搭建、各模块的功能和其配置，特别是核心模块数据处理单元页压缩模块的verilog实现；在页压缩数据处理方面，提出了页压缩的算法及差异数据在HDD中存储的格式，使系统获得较好的数据压缩率。经在FPGA开发板上进行验证，I-CASH页压缩子系统可以正确完成数据页压缩和解压缩。通过修改参考页数据和写入的数据，对各种情况下数据压缩的性能进行了分析。系统整体数据压缩处理速度约为150MB/s。
[Abstract]:Solid State disk disk (SD) storage technology has developed rapidly in recent years and has occupied part of the market with its excellent performance. However, SSD still has a big gap in life and cost compared with hard ware disk driven DDS. The high cost of SSD in the consumer market makes it difficult to popularize, but it is not reliable enough in enterprise application. On the other hand, HDDs are no longer able to meet the system's high speed request for I / O. There is a hybrid storage technology which combines SSD and HDD to achieve the performance close to that of SSD, which has the large capacity of HDD and prolongs the whole life of the system. I-CASHH Intelligent coupled system of SD and HDD is a hybrid storage system that uses SSD and HDD side by side. I-CASH makes use of the principle of content localization of data and stores the data of reference pages that are not changed often in SSD. And only the different data of each data page relative to the reference page is stored in HDD. In this way, the function of data compression is realized relative to HDD, so the system can obtain several times the performance of HDD. In addition, because of the reduction of writing operation to SSD, As a result, the system can also achieve a longer life than the SSD. For the structure design of I-CASH, the implementation scheme of SOC master control chip is used. The main data calculation is accomplished by the special hardware circuit inside the main control chip, while the CPU inside the chip is only responsible for the simple data management. In the implementation of I-CASH system, due to the overall complexity of the scheme, only the design of I-CASH page compression subsystem and its implementation on FPGA are studied deeply, and the structure of the page compression subsystem is given. This paper introduces its construction, function and configuration of each module, especially the verilog implementation of the data processing unit page compression module of the core module, and puts forward the algorithm of page compression and the format of the difference data stored in the HDD in the aspect of page compression data processing. Make the system obtain better data compression ratio. It is verified on the FPGA development board that the compression subsystem of I-CASH pages can correctly complete the compression and decompression of data pages. The performance of data compression in various cases is analyzed. The data compression speed of the whole system is about 150 MB / s.
【学位授予单位】：华中科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333

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