基于Bochs的X86小核前端时序模拟器的设计及优化

发布时间：2018-03-08 01:05

本文选题：Bochs　切入点：跟踪驱动模拟　出处：《北京邮电大学》2012年硕士论文　论文类型：学位论文

【摘要】：体系结构软件模拟技术是使用软件的方式来模拟计算机系统硬件在系统结构级别的功能和性能特性。在现代计算机系统的设计和制造中,使用体系结构软件模拟技术来对体系结构设计进行评估和验证己成为一个不可缺少的环节。本文研究了X86小核处理器的前端设计结构,并在此基础上设计了一个时序模拟器。该时序模拟器以跟踪驱动模拟技术为理论依据,与Bochs模拟器相结合,实现了一个可以执行X86指令的时序模拟器。在模拟器的设计完成后,我们选取SPEC CPU2006中的perlbench测试集作为负载,对时序模拟器进行了验证。通过对事件统计信息及测试集IPC的分析,我们发现了X86小核前端时序模拟器存在性能缺失,并结合X86小核前端设计结构找到了导致时序模拟器性能缺失的原因。为了提高X86小核前端时序模拟器的性能,本文进一步提出了一种加快trace生成速度的方法。该方法通过修改Bochs模拟器中的数据结构而实现,最终使X86小核前端时序模拟器的模拟速度达到每秒500K个处理器周期,这一速度很好地满足了设计需求。综上所述,我们可以发现基于Bochs的X86小核前端时序模拟器不但能够指导X86小核处理器的设计,而且能够成为其性能评估及优化的工具,这对X86小核处理器的设计有着重要的理论意义和使用价值。
[Abstract]:Architecture of software simulation technology is the function and performance characteristics of the way of using the software to simulate the computer system hardware in the system level. In the design and manufacturing of modern computer system, using the software architecture of system simulation technology to design the structure of the assessment and verification has become an indispensable link.
This paper studies the structure of front-end design of X86 single core processor, and on the basis of the design of a timing simulator. The timing simulator using trace driven simulation technology as the theoretical basis, combined with the Bochs simulator, can achieve a X86 instruction timing simulator.
The complete design of the simulator, we select SPEC CPU2006 in the perlbench test set as a load of timing simulator is verified. Through the information and statistics on the test set of events of IPC analysis, we found X86 small front timing simulator performance loss, and the combination of X86 small front design structure found the cause of timing simulator performance missing.
In order to improve the performance of X86 small front timing simulator, this paper proposes a method of accelerating trace generation speed. The method is accomplished by modifying the data structure of Bochs simulator, the simulation speed of the X86 small front timing simulator per second 500K processor cycles, the speed is very good to meet the design requirements.
To sum up, we can find the design guidelines for X86 single core processor can not only X86 small front timing simulator based on Bochs, and can become a tool for performance evaluation and optimization, the X86 single core processor design has important theoretical significance and practical value.

【学位授予单位】：北京邮电大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332

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