高性能CPU中高速接口IP核的DFT集成设计和验证

发布时间：2018-03-09 21:06

本文选题：高速接口IP核　切入点：JTAG　出处：《国防科学技术大学》2012年硕士论文　论文类型：学位论文

【摘要】：目前，为了加快芯片的设计效率和缩短设计周期，IP(Intellectual Property)核的可复用技术是SoC(System on Chip)设计的发展趋势。尤其是高速接口IP核的复用，在不清楚其内部具体设计和结构的情况下，只能把它们当成黑盒子，在集成时其输入输出端口也被嵌入到SoC中，这样原本可测的端口就失去了其原有的可控制性和可观测性，从而变得不可测。这就给高性能CPU的DFT(Design For Testability)集成设计和验证带来了挑战。本文的主要工作是：针对一款高性能CPU芯片（FX芯片）中使用的高速接口IP核进行了自身和将它们集成到CPU中后的DFT集成设计和验证，包括高速串口硬核PCIE2/SATA2/USB2PHY和可以综合的高速并口软核DDR3PHY。先验证设计好的JTAG(Joint Test Action Group)、BIST(Built-In Self Test)等功能的正确性，再从JTAG接口加载测试码启动BIST逻辑进行内外部loopback功能的验证。分别给出了这些IP核的DFT结构设计、验证方法和验证结果。本文工作说明了如何确保IP核自身的正确性，，如何使用其进行有效的集成，如何确保所加载的测试码有效，最终能降低测试难度和测试成本。本文的创新点和难度体现在如下几个方面： 1、综合运用JTAG和BIST技术进行内外部loopback功能的DFT验证，为验证高速接口IP核的模拟和数字路径提供了有效的方法。通过这种方法，能确保它们收发功能的正确性。此外，验证结果还表明，USB2.0nanoPHY能正常运行在低速、高速和全速BIST三种模式。 2、通过编写Testbench，验证了PCIE2PHY中JTAG指令功能的正确性。通过实验，发现了提供的PCIE2PHY的USERCODE指令实际实现的是BYPASS的功能，以及DSCAN指令提供的数据寄存器位数有误，实际应为3209位。 3、对DDR3PHY进行综合后的物理设计时，由于布局布线不够合理，使得DDR3PHY的工作频率会降低。针对这种情况，在验证时采用降低JTAG的测试时钟频率的方法，再去采样DDR3PHY的数据，得到的测试码仍能使其在测试时正常工作。本文所做工作已用于FX芯片设计，且目前FX芯片正处于流片阶段，本文的研究工作不仅能确保这些高速接口IP核的DFT结构设计合理，收发模块功能正确，而且对于相关的工程问题也有借鉴意义。
[Abstract]:At present, in order to speed up the design efficiency of the chip and shorten the design cycle, the reusable technology of IP intellectual property core is the development trend of SoC(System on chip design. They can only be treated as black boxes, and when integrated, their input and output ports are embedded in the SoC, so that otherwise testable ports lose their original controllability and observability. This makes it unfathomable. This poses a challenge to the design and validation of DFT(Design For Testability for high performance CPU. The main work of this paper is to design and verify the high speed interface IP core which is used in a high performance CPU chip (FX chip) and to integrate them into CPU. It includes high speed serial port hard core PCIE2/SATA2/USB2PHY and high speed parallel port soft core DDR3PHY. first verify the correctness of the designed JTAG(Joint Test Action Group in Self Test, etc. Then loading test code from the JTAG interface to start the BIST logic to verify the internal and external loopback functions. The DFT structure design, verification method and verification results of these IP cores are given respectively. The work of this paper shows how to ensure the correctness of the IP core itself. How to use it for effective integration and how to ensure that the loaded test code is effective can reduce the difficulty and cost of testing. The innovation and difficulty of this paper are reflected in the following aspects:. 1. The DFT verification of internal and external loopback functions by using JTAG and BIST technology synthetically provides an effective method for verifying the analog and digital paths of IP cores with high speed interface. By this method, the correctness of their transceiver functions can be ensured. The results also show that USB2.0 nanoPHY can operate in three modes: low speed, high speed and full speed BIST. 2. The correctness of the function of JTAG instruction in PCIE2PHY is verified by writing Testbench.Through experiment, it is found that the USERCODE instruction provided by PCIE2PHY realizes the function of BYPASS, and the number of data registers provided by DSCAN instruction is incorrect, which should be 3209bit. 3. When the physical design of DDR3PHY is synthesized, the working frequency of DDR3PHY will be reduced because the layout and wiring is not reasonable. In view of this situation, the method of reducing the test clock frequency of JTAG is adopted in the verification, and then the data of DDR3PHY is sampled. The obtained test code can still work properly during the test. The work done in this paper has been used in the design of FX chip, and the current FX chip is in the stage of stream chip. The research work in this paper can not only ensure that the DFT structure of the IP core with high speed interface is reasonable, but also the function of the transceiver module is correct. And for the relevant engineering problems also have reference significance.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP334.7;TN47

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