基于SystemC的MIPS处理器建模与架构

发布时间：2018-03-13 10:25

本文选题：SystemC　切入点：系统建模　出处：《计算机工程与设计》2015年04期 　论文类型：期刊论文

【摘要】：为研究系统建模应用于处理器架构设计、性能分析的方法,基于SystemC建模语言,提出一种"结构框图-模块细化-模型映射"自顶向下规范化的系统模型建立方法,以此方法建立MIPS(microprocessor without interlocked piped stages)架构处理器的周期精确模型。研究用系统级模型进行系统架构设计的方法,分析不同高速缓存Cache的设计对处理器性能的影响。仿真结果表明,L1(Level 1)级Cache采用2路或4路、容量在4KB到32KB之间比较合适。
[Abstract]:In order to study the application of system modeling in processor architecture design and performance analysis, based on SystemC modeling language, a top-down normalization method of "structure block diagram, module thinning and model mapping" is proposed. In this way, the cycle exact model of MIPS(microprocessor without interlocked piped piped processor is established, and the method of system architecture design based on system-level model is studied. The effect of different cache Cache design on processor performance is analyzed. The simulation results show that L1 level 1) level 1 Cache adopts 2 or 4 channels, and its capacity is between 4 KB and 32 KB.
【作者单位】：中国航天科工集团第二研究院706所;
【分类号】：TP332

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