FPGA中BRAM的设计

发布时间：2018-03-18 13:40

本文选题：静态存储单元　切入点：静态噪声容限　出处：《西安电子科技大学》2012年硕士论文　论文类型：学位论文

【摘要】：随着集成电路设计水平的提高，对存储器高速、低功耗的需求也越来越高。因此，本文在分析virtexII型FPGA的体系结构的基础上，采用SMIC0.12μm工艺设计了一款块状存储器BlockRAM，，重点研究了BRAM主要模块静态存储单元、灵敏放大器以及外围电路。文中设计了一种适用于双端口存储器的8T SRAM存储单元结构。这种8TSRAM存储单元的静态噪声容限可达到515mV，单元结构抗噪声能力是同尺寸条件下6T SRAM存储单元的1.27倍。文中对传统差分锁存型灵敏放大器的结构做了优化设计，设计中引入了预充电电路和平衡管电路。优化后的灵敏放大器数据读取速度仅需176ps，读取速度是传统差分锁存型灵敏放大器的2倍。文中还对BRAM的主要外围电路做了设计分析，在读写控制电路中引入了小脉冲控制电路，小脉冲宽度可以达到0.842ns。由读写控制电路产生的小脉冲信号作为存储器的内部控制时钟可以有效的提高电路稳定性。文中分别采用NC_verilog和nanosim对所设计的BRAM进行了仿真，结果表明文中设计的双端口存储器可以被配置成数据位宽可选的读写、只读或者只写多种操作模式。大量仿真结果表明文中设计的双端口存储器性能良好，能够在千万门系统级FPGA芯片中稳定工作。
[Abstract]:With the improvement of IC design level, the demand for high speed and low power consumption of memory is becoming higher and higher. Therefore, based on the analysis of the architecture of virtexII type FPGA, A block memory Block RAM (Block RAM) is designed using SMIC0.12 渭 m technology. The main modules of BRAM, such as static memory cell, sensitive amplifier and peripheral circuit, are studied emphatically. In this paper, an 8TSRAM memory cell structure suitable for dual-port memory is designed. The static noise tolerance of the 8TSRAM memory cell can reach 515mV, and the anti-noise capability of the cell structure is 1.27 times that of the 6T SRAM memory cell with the same size. In this paper, the structure of the traditional differential latch sensitive amplifier is optimized. The precharge circuit and the balance tube circuit are introduced in the design. The data reading speed of the optimized sensitive amplifier is only 176 pss. the reading speed is 2 times that of the traditional differential latch sensitive amplifier. The main peripheral circuits of BRAM are also designed and analyzed. The small pulse control circuit is introduced into the read / write control circuit, and the small pulse width can reach 0.842 ns.The small pulse signal generated by the read / write control circuit as the internal control clock of the memory can effectively improve the stability of the circuit. In this paper, NC_verilog and nanosim are used to simulate the designed BRAM, and the results show that the dual-port memory can be configured to read and write the data bit width. A large number of simulation results show that the dual-port memory designed in this paper has good performance and can work stably in tens of millions of system-level FPGA chips.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333

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