32Kb RRAM芯片设计及版图优化

发布时间：2018-03-21 00:41

本文选题：阻变存储器　切入点：存储单元　出处：《复旦大学》2013年硕士论文　论文类型：学位论文

【摘要】：随着特征尺寸的不断减小,传统的Flash会遇到其工艺瓶颈。寻找下一代新型存储器成为研究的热点。在众多下一代非易失性存储器中,阻变存储器(RRAM)由于其逻辑兼容性、编程电压低、易于高密度集成等优点迅速成为下一代新型存储器的有力竞争者。 RRAM芯片为全定制设计,其存储单元的版图结构和其他模块版图的布局、布线,都会严重影响到芯片面积和阻变性能,所以设计出良好的阻变存储器的版图对整个芯片的设计有着极其重要的影响。针对这种情况,本文主要研究RRAM芯片的版图设计,在此基础上研究阻变单元编程电压、高低阻分布、数据保持能力等的关系,并对其进行了优化,最终使芯片面积和性能达到最优。本文设计了一款容量为32kb,阻变材料为WOx,采用1T1R结构的阻变存储器。主要内容有：首先分析芯片设计目标和要求,其次分析选取合适的选通管并设计最小尺寸的RRAM cell的结构,再根据cell结构,考虑寄生参数如寄生电阻、寄生电容的影响,设计面积和可靠性折中的阵列结构。然后由设计要求设计最简单、可靠性最高的外围电路包括行列译码器、DMA等模块,并仿真验证。总拼时使行列译码器与阵列节点匹配和各模块的版图拼接时优化布局,使得面积最小。最后介绍了I/O PAD的选取和testkey的设计。最终芯片在HHNEC0.5um工艺线上流片。通过对芯片的测试,阻变单元性能良好,高低阻窗口可达到10倍以上,编程电压和数据保持能力均达到初始设计和实际应用要求。说明良好的版图设计可以使芯片的面积得到优化,性能得到保障。
[Abstract]:With the decrease of feature size, the traditional Flash will meet with its technological bottleneck. Finding the next generation of new memory has become a research hotspot. In many of the next generation non-volatile memory, resistive memory (RRAM) is due to its logical compatibility. The advantages of low programming voltage and easy high density integration have become powerful competitors for the next generation of memory. The RRAM chip is designed for full customization. The layout structure of the memory unit and the layout and wiring of other modules will seriously affect the chip area and resistive performance. Therefore, the design of good resistive memory layout has an extremely important impact on the design of the whole chip. In view of this situation, this paper mainly studies the layout design of RRAM chip, on the basis of which, the programming voltage of resistive unit is studied. The relationship between high and low resistive distribution, data retention ability and so on is optimized, and the chip area and performance are optimized. In this paper, a kind of resistive memory with 32kb capacity, WOx-resistant material and 1T1R structure is designed. The main contents are as follows: firstly, the design objectives and requirements of the chip are analyzed; secondly, the structure of the RRAM cell with the minimum size is analyzed and the appropriate gating tube is selected. Then according to the cell structure, considering the parasitic parameters such as parasitic resistance, parasitic capacitance, design area and reliability of the eclectic array structure. The peripheral circuit with the highest reliability includes the modules such as the row and row decoder and DMA, and the simulation verifies that the total spell time makes the row and column decoder match with the array node and the layout of each module is optimized. Finally, the selection of I / O PAD and the design of testkey are introduced. Finally, the chip flows on the HHNEC0.5um process line. By testing the chip, the performance of the resistive unit is good, and the high and low resistive window can reach more than 10 times. Both the programming voltage and the data retention ability meet the requirements of initial design and practical application. It is shown that good layout design can optimize the chip area and ensure the performance.
【学位授予单位】：复旦大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333

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