基于65纳米SRAM的高速灵敏放大器的设计与实现

发布时间：2018-03-23 18:37

本文选题：灵敏放大器　切入点：高速　出处：《安徽大学》2012年硕士论文

【摘要】：灵敏放大器因为具有检测小摆幅信号并可以将其快速放大为全摆幅逻辑信号的功能,所以已经被广泛运用于各种数字及模拟电路中,例如存储器(SRAM、 DRAM、Flash)、A/D转化器、数据接收器、片上收发器等。根据不同的应用领域,其结构略有不同,本文从提高SRAM存取速度的角度出发,重点研究了SRAM系统中的关键模块——灵敏放大器,在此基础上设计出了一种新型结构的高速灵敏放大器和提出了一种新型灵敏放大器失调电压的减小技术,并将该技术运用于一款512words×32bits的高速SRAM设计中。灵敏放大器的设计主要需要考虑失调、速度、功耗、面积和良率等指标,其中失调是其最重要的参数。随着半导体工艺技术的不断进步,工艺误差更容易导致器件的失配,由此更容易引起小摆幅输入信号被灵敏放大器错误放大,因此这对灵敏放大器的设计提出了更高的要求。本文首先分析了新工艺下灵敏放大器的设计重点和难点,然后分析了几种常用结构灵敏放大器的优缺点。针对两种常用结构灵敏放大器存在的优缺点,本文提出了一种新型结构的高速灵敏放大器,在SMIC65nm工艺下的仿真结果表明,对比结构一及二型灵敏放大器,与新型结构灵敏放大器连接的位线对形成相同差分电压的延时最小,其延时最大可减小18.26%;在相同仿真条件下,放大300mV差分电压,相比结构一型灵敏放大器,新型结构灵敏放大器速度可提高25.62%～50.38%,能耗可减小18.31%～27.72%；相比结构二型灵敏放大器,新型结构灵敏放大器速度可提高47.56%～58.72%,能耗可减小19.63%～44.98%。针对工艺进步导致失调增大的情况,本文提出了一种用于降低灵敏放大器失调电压,提高SRAM读操作速度的技术。所提出的失调电压减小方案在不需要任何面积补偿的前提下便能大幅度减小灵敏放大器的失调,并提高SRAM的读操作速度,通过仿真验证,当使能信号电压值减小至0.6V时,两种灵敏放大器失调电压的标准偏差减小幅度分别达到31.23%和25.17%；最优点时,与StrongARM SA相连的单列存储阵列总延时减小了14.98%,与Double-tail SA相连的单列存储阵列总延时减小了22.26%；当使能信号电压值为0.6V、位线挂载1024个存储单元时,与StrongARM型灵敏放大器相连的单列存储阵列总能耗减小了30.45%,与Double-tail SA相连的单列存储阵列总能耗减小了29.47%。本文最后将所提出的失调减小技术应用于一款容量为16Kb的SRAM中,前仿真结果Tcq的值介于226.1ps～644.3ps之间,后仿真结果介于644.1ps～1120.2ps之间,都小于1.25ns,完全达到项目指标800MHz～1.25GHz的要求。
[Abstract]:Because of the sensitive amplifier detecting low swing signal and can be quickly enlarged to full swing signal logic function, so it has been widely used in a variety of digital and analog circuits, such as memory (SRAM, DRAM, Flash), A/D converter, data receiver, on-chip transceiver and so on. According to the different application area. Its structure is slightly different, in order to improve the access speed of SRAM point of view, focusing on the key modules of the SRAM system in the sense amplifier, based on the design of a new structure of high speed sensitive amplifier and puts forward a new sense amplifier offset voltage reduction technique, and will use the technology of high speed SRAM design in a 512words * 32bits.
The design of sensitive amplifier mainly need to consider the imbalance, speed, power, area and yield index, the imbalance is the most important parameter. With the development of semiconductor technology, process errors more easily lead to device mismatch, which is more likely to cause small amplitude error sensitive amplifier input signal is amplified, so put forward this is a higher demand for the sense amplifier design.
This paper first analyzes the key and difficulty of sense amplifier design under the new technology, and then analyzes the advantages and disadvantages of several common sense amplifiers. The advantages and disadvantages of two kinds of common sense amplifiers, this paper proposes a new structure of high speed sensitive amplifier, simulation results show that under the SMIC65nm process, and a comparative structure the two sense amplifier, and novel structure of sensitive amplifier connected bit line to form the same differential voltage delay, the maximum time delay can be decreased by 18.26%; in the same simulation conditions, 300mV differential voltage amplifier, a sense amplifier is compared with the structure, the new structure sensitive amplifier speed can be increased to 25.62% ~ 50.38%, the energy consumption can be reduced from 18.31% to 27.72%; compared with the structure of the two sense amplifier, structure sensitive amplifier speed can be increased from 47.56% to 58.72%, the energy consumption can be reduced from 19.63% to 44.98%. According to the technology progress result in disorders of the increase, this paper puts forward a method for reducing the sense amplifier offset voltage, improve the operating speed of the SRAM reading technology. The premise proposed offset voltage reduction scheme does not require any compensation in the area can greatly reduce the imbalance under the sensitive amplifier, and improve the read operation speed of SRAM through the simulation, when the enable signal voltage decreases to 0.6V, two standard deviation sensitive amplifier offset voltage is reduced by 31.23% and 25.17% respectively; the advantages, connected with the StrongARM SA single storage array total delay is reduced by 14.98%, the total delay is connected with the Double-tail SA single memory array is reduced 22.26%; when the enable signal voltage is 0.6V, the bit line mount 1024 storage units, the total energy consumption is connected with the StrongARM type sense amplifier single memory array is reduced by 30.45%, The total energy consumption is connected with the Double-tail SA single memory array is reduced by 29.47%. at the end of this paper, the proposed offset reduction technique applied to a capacity of 16Kb SRAM, the simulation results of Tcq values ranged from 226.1ps to 644.3ps, after the simulation results from 644.1ps to 1120.2ps, are less than 1.25ns, fully meet the project index 800MHz to the requirements of 1.25GHz.

【学位授予单位】：安徽大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333;TN722

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