一种兼容MIPS32指令集的32位软核处理器设计

发布时间：2018-03-31 02:21

本文选题：MIPS32　切入点：软核处理器　出处：《东南大学》2017年硕士论文

【摘要】：本课题研究的是基于MIPS32指令集的32位软核处理器设计,以及基于此处理器的SOPC(System-on-a-Programmable-Chip,可编程片上系统)设计。由于目前国内的CPU内核设计项目比较少,且很少应用到工程实践中,因此课题的研究是为了将自主设计的兼容MIPS32指令的32位CPU内核通过软核的形式,嵌入到FPGA芯片中,实现片上集成控制、数据处理等单元,通过设计软件代码,实现真正意义上的应用。课题的实用意义在于,不仅可以用作教学研究,更可以配合一些外设控制器IP核和总线技术,实现自由定制CPU,通过FPGA实现在具体的硬件上,能够应用到具体的工程项目中。本课题完成了 MIPS32指令集以及相应的架构研究,设计了处理器的五级流水线,包括取指、译码、执行、访存和回写。项目设计了兼容MIPS32指令集的处理器结构,实现了逻辑操作指令、移位操作指令、空指令、移动操作指令、算术操作指令、转移指令、加载存储指令,实现了协处理器和异常的相关处理过程。项目对处理器进行了Wishbone总线的封装,添加了基本的外设控制器,如Flash、SDRAM、GPIO、UART等外设控制器,实现了仿真测试到硬件运行的过程。经过ModelSim软件的仿真测试,可以看出系统正确的实现了五级流水线的运行过程。兼容MIPS32指令集的指令,都可以在流水线中正确的进行取指、译码,并在执行过程中正确计算结果,并完成数据的存取。由于指令的特点和流水线的运行结构所引起的指令"相关"问题,也得到了很好的解决。协处理器可以正常的进行系统的控制工作,多种处理器异常也可以得到正确的处理和实现。系统挂载了 Wishbone总线之后,可以配合相关的外设控制器,实现在FPGA芯片上集成片上系统,实现了从软件仿真到硬件运行的过程。
[Abstract]:This paper studies the design of 32-bit soft core processor based on MIPS32 instruction set and the design of SOPC-on-a-Programmable-Chip-based SOPC-on-a-Programmable-Chip processor. Therefore, the purpose of the research is to embed the 32-bit CPU kernel which is compatible with MIPS32 instructions into the FPGA chip in the form of soft core, to realize the integration control, data processing and other units on the chip, and to design the software code. The practical significance of the subject is that it can not only be used as teaching research, but also can cooperate with some peripheral controller IP core and bus technology, realize the free customization of CPU, and realize it on the specific hardware through FPGA. This subject has completed the research of MIPS32 instruction set and the corresponding architecture, designed the five-stage pipeline of processor, including taking finger, decoding, executing, Memory access and write back. The project designs a processor architecture compatible with MIPS32 instruction set. It implements logical operation instruction, shift operation instruction, null instruction, moving operation instruction, arithmetic operation instruction, transfer instruction, loading storage instruction. The project encapsulates the processor with Wishbone bus, and adds basic peripheral controller, such as Flash Wishbone controller, GPIOART controller, etc. Through the simulation test of ModelSim software, we can see that the system has correctly realized the running process of five-level pipeline. The instructions compatible with the MIPS32 instruction set can be correctly used to fetch the finger in pipeline. Decoding, correctly calculating the results during execution, and completing the data access. Due to the characteristics of the instruction and the operation structure of pipeline, the instruction "related" problem, The coprocessor can control the system normally, and various processor exceptions can be handled and implemented correctly. After the system mounts the Wishbone bus, it can cooperate with the related peripheral controller. The system is integrated on FPGA chip and the process from software simulation to hardware operation is realized.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP332

【参考文献】