基于SOC嵌入式处理器调试系统的开发与研究

发布时间：2018-04-01 00:15

本文选题：SOC　切入点：调试　出处：《武汉纺织大学》2013年硕士论文

【摘要】：随着片上系统（SOC）技术的不断发展以及嵌入式系统对处理器处理能力的要求不断提到。32位处理器IP核已经广泛用于SOC及SOPC（硬件可配置SOC）的设计与开发当中，在众多的嵌入式处理器中，专用指令集处理器(ASIP，application Specific in-struction processor)设计是多年来嵌入式系统研究的热点，因为融合了许多先进微处理器设计方法和技术，并可以在满足功能的同时缩短嵌入式微处理的研发时间。但是采用ASIP设计出来的嵌入式系统的复杂度与开发设计难度也会随之不断的增加，这对嵌入式系统的设计与开发提出了新的要求，，所以调试在ASIP的开发中就越来越重要了，随着OCD（On Chip Debugging:在芯片调试）调试方式与SOC技术的出现，完全改变了传统的“仿真器加编程器”的调试方法，通过这种方式可以提高整体调试的效率。本文首先以Openrisc CPU作为嵌入式处理器的研究模型，在这个CPU基础上添加外围接口设计出一个SOC最小系统并在深入研究SOC设计理念和JTAG调试原理后，采用软硬件协同设计方法，充分利用SOC的可重用性与FPGA的可编程性，在SOC系统中利用片上总线技术加入了自己编写的针对SOC嵌入式处理器调试接口的IP core,通过这个IP core可以方便的进行嵌入式处理器的调试以及嵌入式软件的调试。通过采用这种调试方式达到调试SOC硬件也可以调试嵌入式软件的目的。同时在Linux系统中针对ASIP进行Linux系统移植并采用JTAG方式进行系统的下载。
[Abstract]:With the continuous development of on-chip system (SOC) technology and the requirement of embedded system for processor processing capability, the .32-bit processor IP core has been widely used in the design and development of SOC and SOPC (hardware configurable SOCC). Among many embedded processors, the design of ASIP application Specific in-struction processor has been a hot spot in embedded system research for many years, because of the integration of many advanced microprocessor design methods and techniques. It can also shorten the development time of embedded microprocessing while satisfying the function. However, the complexity of embedded system designed by ASIP and the difficulty of developing and designing will increase with it. This has put forward new requirements for the design and development of embedded system, so debugging is becoming more and more important in the development of ASIP. With the emergence of OCD(On Chip debugging (debugging in Chip) and SOC technology, The traditional debugging method of "emulator plus programmer" is completely changed, by which the overall debugging efficiency can be improved. Firstly, Openrisc CPU is used as the research model of embedded processor. On the basis of this CPU, a SOC minimum system is designed by adding peripheral interface. After deeply studying the SOC design concept and JTAG debugging principle, the hardware / software co-design method is adopted to make full use of the reusability of SOC and the programmability of FPGA. In the SOC system, the on-chip bus technology is used to add IP core for the debugging interface of SOC embedded processor, through which the embedded processor can be debugged and embedded software can be debugged conveniently. The embedded software can also be debugged by using this debugging method to debug the SOC hardware. At the same time, the Linux system is transplanted to ASIP in the Linux system and the system is downloaded by JTAG mode.
【学位授予单位】：武汉纺织大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP368.1;TN47

【参考文献】