WCET可预测的嵌入式JavaCPU设计

发布时间：2018-04-03 23:11

本文选题：Java处理器　切入点：RISC　出处：《江南大学》2012年硕士论文

【摘要】：目前,移动互联网技术和市场都出现了爆炸式的增长,随着苹果和android手机为代表的嵌入式便携设备的问世,移动互联网大有代替桌面互联网之势,充分说明了嵌入式设备的发展对我们生活的影响之大。各种嵌入式产品更新换代的速度日新月异,对嵌入式系统的开发效率有非常高的要求。Java作为一种基于网络应用的语言,具有高效性、安全性、良好的可移植性及动态性,因此研究人员迫切希望使用Java来进行嵌入式软件开发。为了满足软件研发人员的需求,各种嵌入式实时Java平台层出不穷。比较常规的实现平台方式有解释方式、提前编译、即时编译、Java硬件加速器、Java处理器等。通过比较各方式的优缺点,以Java处理器方式实现的嵌入式实时Java平台以硬件直接执行Java字节码,执行效率最高。前面的工作中提出了一种32位Java处理器JPOR-32(Java Processor Optimized For RTSJ)的架构,并初步实现了部分部件。本文在此基础上根据Java指令集的字节码执行流程,优化了处理器架构,并完善及扩展了各部件,最后将各模块组合成完整的流水线处理器。具体工作如下: 1.增加了内存模块,多了一级访存的流水段。内存主要以类文件中数据结构为参考实现,可以存放预处理后的类文件,这样使处理器能直接从外部读取Java字节码文件,还能支持跳转分支指令对内存进行跳转读取。 2.添加了连接各模块的控制单元,使处理器能进行流水处理,包括控制所有指令进行相同流水的三段:取指令、指令缓冲、译码,还有指令译码设置的48位控制信号根据不同指令控制执行、访存和写回部件的操作。 3.除了在处理器上实现了简单Java指令,还以微指令方式实现了包括方法调用与返回等用硬件难以直接实现的复杂指令。本文最终在JPOR-32上实现了85条Java指令,使用FPGA对处理器进行了验证,对各指令和应用程序的运行时钟进行了检测。实验结果表明了此处理器比其他Java处理器指令执行周期更短,具有高性能并且其WCET可预测。
[Abstract]:At present, the mobile Internet technology and market have explosive growth. With the advent of embedded portable devices represented by Apple and android mobile phones, mobile Internet has the potential to replace desktop Internet.It fully shows that the development of embedded devices has a great impact on our lives.As a language based on network application, Java has high efficiency, security, good portability and dynamic.So researchers are eager to use Java for embedded software development.In order to meet the needs of software developers, embedded real-time Java platforms emerge in endlessly.The common implementation platform is interpreted, compiled in advance, and Java hardware accelerator / Java processor is compiled in real time.By comparing the advantages and disadvantages of each method, the embedded real-time Java platform implemented by Java processor can execute Java bytecode directly by hardware, and the execution efficiency is the highest.In the previous work, a 32-bit Java processor, JPOR-32(Java Processor Optimized For RTSJ, is proposed, and some components are implemented.On this basis, according to the bytecode execution flow of the Java instruction set, the processor architecture is optimized, and the components are improved and expanded. Finally, the modules are combined into a complete pipeline processor.The specific work is as follows:1.Added to the memory module, more than one level of memory income segment.The memory is mainly realized by reference to the data structure in the class file, which can store the preprocessed class file, so that the processor can directly read the Java bytecode file from the outside, and can also support the jump branch instruction to read the memory.2.A control unit connected to each module is added to enable the processor to handle income, including controlling all instructions to carry out the same three segments of income: take instructions, buffer instructions, decode them.The 48-bit control signal set by instruction decoding controls the operation of execution, memory access and write back components according to different instructions.3.In addition to the simple Java instructions implemented on the processor, complex instructions, including method call and return, which are difficult to implement directly by hardware, are implemented by microinstruction.In this paper, 85 Java instructions are implemented on JPOR-32, the processor is verified by FPGA, and the running clock of each instruction and application program is detected.Experimental results show that the processor has shorter instruction execution period, higher performance and more predictable WCET than other Java processors.
【学位授予单位】：江南大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP368.1;TP332

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