面向粗粒度可重构处理器REMUS-II的任务编译器设计与实现

发布时间：2018-04-05 19:03

本文选题：可重构计算　切入点：粗粒度　出处：《上海交通大学》2012年硕士论文

【摘要】：随着集成电路产业的不断发展，对计算系统高效性和灵活性的需求也不断增加。可重构处理器兼具了专用集成电路的运算高效性与通用处理器的编程灵活性,近年来受到了广泛关注。可重构处理器的典型结构为一个主控制器耦合一个可重构处理单元。可重构处理器的任务编译器可以将计算任务高效地映射到可重构处理单元中，是可重构处理器系统的重要支撑软件。本论文针对粗粒度可重构处理器REMUS-II，设计并实现了一款自动化任务编译器LOOPCC。该任务编译器前端部分从输入的高级语言中自动提取被标记的并行代码段，将其转化为中间表示数据流图(DFG)。任务编译器后端部分将DFG划分为数个较小规模的逻辑子图并将其映射到可重构阵列上，最终生成驱动可重构处理单元的配置信息和用于主控制器的配套代码。本文采用循环部分展开技术解决了编译前端生成DFG规模大、冗余信息多的问题。针对REMUS-II的硬件特点，本文通过使用常数输入提取技术对DFG进行预处理，并采用优化阵列数据流、配置阵列循环复用等手段提高硬件资源利用率，，提高了REMUS-II可重构处理器的运行效率。本论文对LOOPCC进行了功能验证和性能分析。实验数据表明，LOOPCC任务编译器各项功能正确，与REMUS-II系统原有任务编译器相比，编译时间降低28%，配置信息量减少80%，同时还获得了3倍以上的运行性能提升。
[Abstract]:With the development of integrated circuit industry, the demand for high efficiency and flexibility of computing system is increasing.Reconfigurable processors (RCPs), with both high computational efficiency of ASIC and programming flexibility of general-purpose processors, have attracted wide attention in recent years.The typical architecture of a reconfigurable processor is a master controller coupling a reconfigurable processing unit.Task compiler of reconfigurable processor can efficiently map computing task to reconfigurable processing unit, which is an important supporting software for reconfigurable processor system.In this paper, an automatic task compiler LOOPC is designed and implemented for the coarse grained reconfigurable processor REMUS-II.The front-end part of the task compiler automatically extracts the tagged parallel code segment from the input high-level language and converts it into an intermediate representation data flow graph (DFG).In the back-end part of the task compiler, the DFG is divided into several smaller logical subgraphs and mapped to the reconfigurable array, and the configuration information of the driving reconfigurable processing unit and the supporting code for the main controller are generated.In this paper, the problem of large scale and redundant information of compiling front end generated DFG is solved by using cyclic partial expansion technique.In view of the hardware characteristics of REMUS-II, this paper uses constant input extraction technology to pre-process DFG, optimizes array data flow, configures array cycle reuse and so on to improve the utilization ratio of hardware resources.The efficiency of REMUS-II reconfigurable processor is improved.In this paper, the function verification and performance analysis of LOOPCC are carried out.The experimental data show that all functions of the task compiler are correct. Compared with the original task compiler of REMUS-II system, the compilation time is reduced by 28%, the amount of configuration information is reduced by 80%, and the running performance is improved by more than 3 times.
【学位授予单位】：上海交通大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332

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