层次化架构嵌入式多核处理器原型设计及其编程研究

发布时间：2018-04-17 13:21

本文选题：层次化 + 多核处理器　；参考：《合肥工业大学学报(自然科学版)》2014年11期

【摘要】：VLSI技术进步和应用驱动使多核技术成为主流的微处理器设计技术。多核处理器作为一种时空域器件,应把超级计算机作为多核处理器的设计参考系,其主流架构将最终收敛到"小核、大阵列、层次化"上。文章利用Xilinx Virtex5-330TFPGA器件,设计实现了一款集成16个处理核的具备层次化架构特征的嵌入式多核处理器原型芯片,工作频率为90 MHz。多核处理器利用层次化的体系架构、灵活的片上互连、多种同步机制以及合理的并行程序模型,成功加载了实时视频淡入淡出(fade-in-fade-out)混叠应用(320×240,30帧/s)。基于该多核处理器架构,研究比较了粗粒度和细粒度2种并行编程模型。细粒度模型的多核同步操作稍复杂,但很好地掩盖了应用的串行操作时间,对视频淡入淡出混叠应用的加速比可达6.97。
[Abstract]:Advances in VLSI technology and application drive make multi-nuclear technology the mainstream of microprocessor design technology.As a kind of space-time device, the supercomputer should be regarded as the design reference system of the multi-core processor, and its main architecture will eventually converge to "small core, large array, hierarchical".In this paper, an embedded multi-core processor prototype chip with hierarchical architecture and 16 processing cores is designed and implemented using Xilinx Virtex5-330TFPGA device. The working frequency is 90 MHz.Using hierarchical architecture, flexible on-chip interconnection, multiple synchronization mechanisms and a reasonable parallel program model, the multicore processor successfully loads a real-time video fade in and out of the fafade-in-fade-out) aliasing application of 320 脳 24030 frames / sg.Based on the multi-core processor architecture, two parallel programming models, coarse-grained and fine-grained, are studied and compared.The multi-core synchronous operation of the fine-grained model is a little complicated, but it can cover up the serial operation time of the application, and the speedup of the video fade in and out of the aliasing application can reach 6.97.
【作者单位】：河南城建学院电气与信息工程学院;合肥工业大学微电子设计研究所;
【基金】：国家自然科学基金资助项目(61179036;61106020)
【分类号】：TP332

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