定点小数乘法器的低功耗算法与实现技术

发布时间：2018-04-17 17:43

本文选题：定点小数乘法 + 加法器数量　；参考：《中南大学学报(自然科学版)》2014年01期

【摘要】：针对集成电路前端设计中的定点小数乘法器,提出一种既能够优化其内部加法器数量又能优化各级加法结果位宽的低功耗算法,而且在算法的实现技术上,解决目前低功耗设计中算法自身逻辑单元引入被优化系统从而降低系统优化效果的问题。在介绍该算法的理论基础和实现细节后,为了取得更加客观、更具有统计特性的低功耗优化效果,以该算法对某含有大量不同类型小数乘法器的射频模块进行优化。优化后FPGA测试结果显示逻辑占用率降低了39.3%,寄存器总数降低了45.0%,内存占用率降低了36.9%。该算法是一种高效的低功耗算法,并且解决了一般算法实现技术的缺陷与不足,其适用于对含有大量小数乘法运算的系统进行低功耗优化,例如数字信号处理和数字滤波器等。
[Abstract]:Aiming at the fixed-point decimal multiplier in the front-end design of integrated circuit, this paper proposes a low power algorithm which can optimize the number of internal adders and optimize the bit width of all levels of addition results.To solve the problem that the logic unit of the algorithm itself is introduced into the optimized system in the low power design at present, which reduces the optimization effect of the system.After introducing the theoretical basis and implementation details of the algorithm, in order to achieve more objective and more statistical characteristics of low power optimization effect, the algorithm is used to optimize a radio frequency module with a large number of different types of fractional multipliers.The optimized FPGA test results show that the logic occupancy rate is reduced by 39.3, the total number of registers is reduced by 45.0 and the memory occupancy rate is reduced by 36.9 percent.This algorithm is an efficient low-power algorithm, and solves the shortcomings and shortcomings of the general algorithm implementation technology. It is suitable for low-power optimization of systems with a large number of decimal multiplication operations, such as digital signal processing and digital filter.
【作者单位】：西安电子科技大学微电子学院宽禁带半导体材料与器件国家重点实验室;
【基金】：国家自然科学基金资助项目(60976068) 教育部科技创新工程重大项目培育资金资助项目(708083) 教育部博士点基金资助项目(200807010010)
【分类号】：TP332.2

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